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18th international conference on field programmable and logic applications

作者： Brunelli, Claudio Garzia, Fabio Giliberto, Carmelo Nurmi, Jari Tampere Univ Technol Dept Informat Technol Inst Digital & Comp Syst FIN-33101 Tampere Finland

ISBN: (纸本)9781424419609

A very common problem which affects the performance of bus-based computing systems arises from the fact that the bus is a common resource which needs to be shared between a number of master devices. the common resource contention forces to stall temporarily the execution of one or more of the bus masters, slowing down the execution. Moreover, the width of the bus is usually relatively small, forcing the bus master to perform several bus cycles in order to transfer a data block from the main memory to a peripheral (or to a processing element), and the other way around. ne combination of these factors leads to problems and inefficiencies which designers need to solve. In this paper we present a dedicated hardware used to allow an external accelerator to access the system memory independently from the main microprocessor. the proposed device is able to exchange data with the memory in a DMA-like fashion, to generate properly memory addresses in order to access it in an efficient way. Results show that using such a solution it is possible to reach a considerable speed-up in the execution of a given algorithm.

关键词： Computation theory

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thE EFFECT OF SPARSE SWITCH PATTERNS ON thE AREA EFFICIENCY OF MULTI-BIT ROUTING RESOURCES IN field-programmable GATE ARRAYS

THE EFFECT OF SPARSE SWITCH PATTERNS ON THE AREA EFFICIENCY ...

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18th international conference on field programmable and logic applications

作者： Chen, Ping Ye, Andy Ryerson Univ Dept Elect & Comp Engn Toronto ON M5B 2K3 Canada

ISBN: (纸本)9781424419609

the increased use of multi-bit processing elements such as digital signal processors, multipliers, multi-bit addressable memory cells, and CPU cores has presented new opportunities for field-programmable Gate Array (FPGA) architects to utilize the regularity of multi-bit signals to increase the area efficiency of FPGAs. In particular, configuration memory sharing has been traditionally used to exploit multi-bit regularity for area. We observe that the process of creating configuration memory sharing routing resources often leads to the use of much sparser switch patterns for connecting multi-bit elements to their routing tracks. In this work, we empirically evaluate the effect of these sparse switch patterns on the area efficiency of FPGAs. It is shown that the sparse switch patterns alone contribute significantly to the area reduction observed in configuration memory sharing FPGAs. In particular, our experiments show that, without configuration memory sharing, sparse switch patterns can reduce the implementation area of multi-bit routing resources by 10.4% while configuration memory sharing contributes to an additional 1.2% in area savings. the observation holds over a wide range of connection block flexibility values and demonstrates that efficient switch pattern designs can be effectively used to increase the area efficiency of FPGA routing resources.

关键词： field programmable gate arrays (FPGA)

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DECIMAL MULTIPLIER ON FPGA USING EMBEDDED BINARY MULTIPLIERS

DECIMAL MULTIPLIER ON FPGA USING EMBEDDED BINARY MULTIPLIERS

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18th international conference on field programmable and logic applications

作者： Neto, Horacio C. Vestias, Mario R. Univ Tecn Lisboa INESC ID IST UTL P-1100 Lisbon Portugal Polytech Inst Lisbon INESC ID ISEL IPL Lisbon Portugal

ISBN: (纸本)9781424419609

Decimal arithmetic has become a major necessity in computer arithmetic operations associated with human-centric applications, like financial and commercial, because the results must match exactly those obtained by human calculations. the relevance of decimal arithmetic has become evident with the revision of the IEEE-754 standard to include decimal floating-point support. there are already a variety of IP cores available for implementing binary arithmetic accelerators in FPGAs. thus far, however, little work has been done with regard to implementing cores that work with decimal arithmetic. In this paper, we introduce a novel approach to the design of a decimal multiplier in FPGA using the embedded arithmetic blocks and a novel method for binary to BCD conversion. the proposed circuits were implemented in a Xilinx Virtex 4sx35ff877-12 FPGA. the results indicate that the proposed binary to BCD converter is more efficient than the traditional shift and add-3 algorithm and that the proposed decimal multiplier is very competitive when compared to decimal multipliers implemented with direct manipulation of BCD numbers.

关键词： field programmable gate arrays (FPGA)

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FILE SYSTEM ACCESS FROM RECONFIGURABLE FPGA HARDWARE PROCESSES IN BORPH

FILE SYSTEM ACCESS FROM RECONFIGURABLE FPGA HARDWARE PROCESS...

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18th international conference on field programmable and logic applications

作者： So, Hayden Kwok-Hay Brodersen, Robert Univ Hong Kong Dept Elect & Elect Engn Hong Kong Hong Kong Peoples R China Univ Calif Berkeley Dept Comp Sci & Elect Engn Berkeley CA 94720 USA

ISBN: (纸本)9781424419609

this paper presents the design and implementation of BORPH's kernel file system layer that provides FPGA processes direct access to the general file system. Using a semantics resembling that of conventional UNIX file I/Os, an FPGA accesses the file system through a special hardware system call interface. By extending the semantics of a UNIX pipe, a single file system access mechanism is used for both regular file I/O, as well as for hardware/software and hardware/hardware data streaming. An FPGA design may switch between different communication modes dynamically during run time by means of file redirection. Design trade-offs among system manageability, user usability and application performance are explored. An example of constructing a video processing system during run time using commodity software and FPGA applications connected by pipes is used to demonstrate the feasibility and potential of such FPGA-centric file system access capability.

关键词： field programmable gate arrays (FPGA)

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APPLICATION-ADAPTIVE RECONFIGURATION OF MEMORY ADDRESS SHUFFLER FOR FPGA-EMBEDDED INSTRUCTION-SET PROCESSOR

APPLICATION-ADAPTIVE RECONFIGURATION OF MEMORY ADDRESS SHUFF...

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18th international conference on field programmable and logic applications

作者： Kwon, Young-Su Koo, Bon-Tae Eum, Nak-Woong Elect & Telecommun Res Inst SoC Res Dept Applicat SoC Dev Team Taejon 305606 South Korea

ISBN: (纸本)9781424419609

Programmability requirement in reconfigurable systems necessitates the integration of soft processors in FPGAs. the extensive memory bandwidth sets a major performance bottleneck in soft processors for media applications. While the parallel memory system is a viable solution to account for a large amount of memory transactions in media processors, the memory access conflicts caused by multiple memory buses limit the overall performance. We propose and evaluate the configurable memory address shuffler to be integrated in the memory access arbiter for the parallel memory system in a soft processor. the novel address shuffling algorithm reallocates the decomposed memory sub-pages based on the access conflict graph obtained by profiling the memory access pattern of the application to produce the synthesizable code. the address shuffler efficiently translates the requested memory addresses into the shuffled addresses such that the amount of simultaneous accesses to the identical physical memory block diminishes. the reconfigurability of the address shuffler enables the adaptive address shuffling depending on the memory access pattern of an application running on the soft processor. the configurable address shuffler reduces the amount of access conflicts by 80% on average utilizing 1592 LUTs which is 14% of that of the processor.

关键词： field programmable gate arrays (FPGA)

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HIGH-SPEED REGULAR EXPRESSION MATCHING ENGINE USING MULTI-CHARACTER NFA

HIGH-SPEED REGULAR EXPRESSION MATCHING ENGINE USING MULTI-CH...

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18th international conference on field programmable and logic applications

作者： Yamagaki, Norio Sidhu, Reetinder Kamiya, Satoshi NEC Corp Ltd Syst IP Core Res Labs Kawasaki Kanagawa Japan Satyam Comp Serv Ltd Appl Res Grp Bangalore Karnataka India

ISBN: (纸本)9781424419609

An approach is presented for high throughput matching of regular expressions (regexes) by first converting them into corresponding Non-deterministic Finite Automata (NFAs) which are then configured onto a FPGA. the key novel feature is a technique that, for any given regex, constructs an NFA that processes multiple characters per clock cycle. An efficient algorithm is proposed that outputs an NFA which processes twice the number of characters as the input one. A technique is also proposed that implements the range match operation (e.g. [a-z]) efficiently. A program has been written that implements above ideas to convert regexes into NFAs specified in a structural Hardware Design Language (HDL), which are then mapped onto a FPGA. Performance is evaluated using real world regexes (Snort ruleset). the results demonstrate the practical utility of the approach. For example, for a set of 2,691 regexes, while the standard 1-character NFA obtains a throughput of 1.25 Gbps, our 4-character NFA achieves a throughput of 3.63 Gbps, while requiring only 20% more LUTs and 6% less flip-flops.

关键词： field programmable gate arrays (FPGA)

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MetaWire: using FPGA configuration circuitry to emulate a network-on-chip

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IET COMPUTERS AND DIGITAL TECHNIQUES 2010年第3期4卷 159-169页

作者： Shelburne, M. Patterson, C. Athanas, P. Jones, M. Martin, B. Fong, R. Virginia Tech Bradley Dept Elect & Comp Engn Configurable Comp Lab Blacksburg VA 24061 USA

Although there have been many reported implementations of networks-on-chip (NoCs) on FPGAs, they have not seen the same acceptance as NoCs on ASICs. One reason is that communication on a field programmable gate array (FPGA) is already costly because of the die resources and time delays inherent in the reconfigurable structure. Layering another general-purpose network on top of the reconfigurable network simply incurs too many performance penalties. there is, however, already a largely unused, global network available in FPGAs. As a proof-of-concept, we demonstrate that the Xilinx FPGA configuration circuitry, which is normally idle during system operation, can function as a relatively high-performance NoC. MetaWire performs transfers through an overclocked Virtex-4 internal configuration access port and is shown to provide a bandwidth exceeding 200 MB/s.

关键词： NETWORKS on a chip field programmable gate arrays APPLICATION-specific integrated circuits BANDWIDthS EMBEDDED computer systems

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TOWARDS AN "EARLY NEURAL CIRCUIT SIMULATOR": A FPGA IMPLEMENTATION OF PROCESSING IN thE RAT WHISKER SYSTEM

TOWARDS AN "EARLY NEURAL CIRCUIT SIMULATOR": A FPGA IMPLEMEN...

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18th international conference on field programmable and logic applications

作者： Leung, Brian Pan, Yan Schroeder, Chris Memik, Seda Ogrenci Memik, Gokhan Hartmann, Mitra J. Z. Northwestern Univ Dept Elect Engn & Comp Sci 2145 Sheridan Rd Evanston IL 60208 USA Northwestern Univ Dept Biomed Engn Evanston IL 60208 USA Northwestern Univ Dept Mech Engn Evanston IL 60208 USA

ISBN: (纸本)9781424419609

We have constructed a FPGA-based "early neural circuit simulator" to model the first two stages of stimulus encoding and processing in the rat whisker system. Rats use tactile input from their whiskers to extract object features such as size and shape. We use the simulator to examine the plausibility of the hypothesis that neural circuits in the rat's brain compute gradients of radial distance across the whisker array to make predictions about the environment. this prediction could be a component of a feed-forward signal that guides the navigation behavior of the rat. the use of a FPGA is highly suitable for such an application, because the computation involved in this system is a massively parallel problem. For our applications, we determined that a Cyclone 11 FPGA could simulate up to 14 neurons in parallel in just 265 ns achieving a 386-fold speedup over the software implementation of the same model.

关键词： field programmable gate arrays (FPGA)

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PERFORMANCE OPTIMIZATION BY TRACK SWAPPING ON CRITICAL PAthS UTILIZING RANDOM VARIATIONS FOR FPGAS

PERFORMANCE OPTIMIZATION BY TRACK SWAPPING ON CRITICAL PATHS...

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18th international conference on field programmable and logic applications

作者： Sugihara, Y. Kume, Y. Kobayashi, K. Onodera, H. Kyoto Univ Dept Commun & Comp Engn Grad Sch Informat Sakyo Ku Kyoto 6068501 Japan

ISBN: (纸本)9781424419609

Since FPGAs in future deep sub-micron processes will suffer from drastic speed and yield losses caused by device variations, we propose variation-aware reconfiguration that utilizes these variations for performance enhancement. To utilize random variations on a current deep submicron process for performance enhancement, optimizing each device from a common configuration is better than producing optimized configurations based on detailed measurement results. In this paper we apply a track swapping procedure to critical path reconfiguration. First, we configure all fabricated FPGAs with common configuration data. the configuration of each die is optimized to reroute the critical paths that do not satisfy timing specifications. the rerouting of a critical path usually causes serious topology changes that may prolong other paths and create new critical paths. In the track swapping procedure, we swap a wire track on a critical path for the adjacent track without any topology changes by switching blocks with more flexibility. We experiment on performance enhancement by applying track swapping to LGSynth93 benchmark circuits. the average speed enhancement is 2.45%, and the average yield enhancement is 32.7% when the standard deviation of the random variations is 10.0%.

关键词： field programmable gate arrays (FPGA)

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MetaWire: using FPGA configuration circuitry to emulate a network-on-chip

MetaWire: using FPGA configuration circuitry to emulate a ne...

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18th international conference on field programmable and logic applications

作者： Shelburne, M. Patterson, C. Athanas, P. Jones, M. Martin, B. Fong, R. Virginia Tech Bradley Dept Elect & Comp Engn Configurable Comp Lab Blacksburg VA 24061 USA

ISBN: (纸本)9781424419616

关键词： field programmable gate arrays (FPGA)

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