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FPGA implementation of an interior point method for high-speed model predictive control

FPGA implementation of an interior point method for high-spe...

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international conference on field programmable logic and applications

作者： Junyi Liu Helfried Peyrl Andreas Burg George A. Constantinides Department of Electrical and Electronic Engineering Imperial College London United Kingdom ABB Corporate Research Baden-Dattwil Switzerland Telecommunication Circuits Laboratory Ecole Polytechnique Federale de Lausanne (EPFL) Switzerland

In this paper, we present a hardware architecture for implementing an interior point method for model predictive control (MPC) on field programmable gate arrays (FPGA). the FPGA implementation allows the solution of quadratic programs occurring in MPC at very high speed. Experiments show that our hardware implementation is able to outperform an software implementation running on a high-end CPU while consuming significantly less power making it well-suited for embedded industrial control applications. In contrast to existing FPGA implementations, the proposed solution exploits the MPC-specific problem structure with the direct linear equation solver and uses an efficient predictor-corrector algorithm. Moreover, the modular design of the architecture simplifies customization or extension to special control problem classes. the proposed FPGA solution can broaden the applicability of solving complex or large MPC problems in embedded computing platforms that were so far considered out of reach.

关键词： Pipelines Hardware field programmable gate arrays Equations Vectors Optimization Computer architecture

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Run-time accelerator binding for tile-based mixed-grained reconfigurable architectures

Run-time accelerator binding for tile-based mixed-grained re...

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international conference on field programmable logic and applications

作者： Cláudio Machado Diniz Muhammad Shafique Sergio Bampi Jörg Henkel Chair for Embedded Systems (CES) Karlsruhe Institute of Technology (KIT) Germany Institute of Informatics Federal University of Rio Grande do Sul (UFRGS) Brazil

Run-time mixed-grained reconfigurable architectures emerged as an efficient solution to deal with the heterogeneous and at-design-time unpredictable nature of advanced applications. Due to interconnection limitations, the reconfigurable elements are grouped into tiles communicating through an on-chip network. State-of-the-art run-time accelerator binding schemes, i.e., mapping the accelerators to elements in the physical reconfigurable array, do not deal with such tile-based architectures. We propose a new scheme for run-time accelerator binding into our tile-based mixed-grained reconfigurable architecture. By means of an advanced video encoding application, we illustrate that our scheme reduces the inter-tile communication overhead by up to 44% (avg. 23%).

关键词： Reconfigurable architectures Program processors field programmable gate arrays Acceleration Organizations Discrete cosine transforms

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Secure partial dynamic reconfiguration with unsecured external memory

Secure partial dynamic reconfiguration with unsecured extern...

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international conference on field programmable logic and applications

作者： Hirak Kashyap Ricardo Chaves INESC-ID IST Universidade de Lisboa Lisbon Portugal

this paper proposes a solution to improve the security of the partial dynamic reconfiguration of FPGA, without significantly affecting the reconfiguration performance. the existing solutions for secure partial dynamic reconfiguration on SRAM based FPGAs impact the reconfiguration process and the available resources due to their complex multi-layered partial bitstream validation process. this adversely affects the performance of applications using reconfigurable hardware. the proposed solution uses high performance encryption engines to change the encryption key of the remotely received bitstream by a randomly generated key, unique to each configuration, when storing the bitstream in the external unsecured memory. An additional CBC-MAC authentication mechanism is also considered that combined with the frame-wise error detection mechanism of the configuration port, allows for an improved countermeasure against replay attack and wrongful bitstream usage. the proposed solution introduces a resource overhead of 1.1% in regard to the base reconfigurable system and provides the lowest impact on the reconfiguration process when compared to the related state of the art, achieving a reconfiguration throughput of 2.5 Gbps.

关键词： field programmable gate arrays Encryption Authentication Performance evaluation Engines

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Towards dark silicon era in FPGAs using complementary hard logic design

Towards dark silicon era in FPGAs using complementary hard l...

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international conference on field programmable logic and applications

作者： Ali Ahari Behnam Khaleghi Zahra Ebrahimi Hossein Asadi Mehdi B. Tahoori Sharif University of Technology Tehran Tehran IR Karlsruher Institut fur Technologie Karlsruhe Baden-WÃ¼rttemberg DE

While the transistor density continues to grow exponentially in field-programmable Gate Arrays (FPGAs), the increased leakage current of CMOS transistors act as a power wall for the aggressive integration of transistors in a single die. One recently trend to alleviate the power wall in FPGAs is to turn off inactive regions of the silicon die, referred to as dark silicon. this paper presents a reconfigurable architecture to enable effective fine-grained power gating of unused logic Blocks (LBs) in FPGAs. In the proposed architecture, the traditional soft logic is replaced with Mega Cells (MCs), each consists of a set of complementary Generic Reconfigurable Hard logic (GRHL) and a conventional Look-Up Table (LUT). Both GRHL cells and LUTs can be power gated and turned off by controlling configuration bits. In the proposed MC, only one cell is active and the others are turned off. Experimental results on MCNC benchmark suite reveal that the proposed architecture reduces the critical path delay, power, and Power Delay Product (PDP) of LBs up to 5.3%, 30.4%, and 28.8% as compared to the equivalent LUT-based architecture.

关键词： Table lookup logic gates Silicon Delays Benchmark testing Iron

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DyRACT: A partial reconfiguration enabled accelerator and test platform

DyRACT: A partial reconfiguration enabled accelerator and te...

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international conference on field programmable logic and applications

作者： Kizheppatt Vipin Suhaib A. Fahmy School of Computer Engineering Nanyang Technological University Singapore

Integrating FPGAs with a general purpose computer remains difficult, but recent efforts have resulted in open frameworks that offer a software API and hardware interface to allow easier integration. However, such systems only support static FPGA designs. With the addition of partial reconfiguration (PR) support, such frameworks can enable more effective use of FPGAs. Now, designers can incorporate hardware accelerators within their software applications, and these can be loaded dynamically as required. We present a PR-enabled FPGA platform that allows user modules to be loaded onto the FPGA, inputs to be applied, results obtained, and functions to be swapped at runtime. the interface and PR management logic are part of the static region, while multiple accelerators can be loaded using high level functions provided by the API. Reconfiguration and data transfer are both managed over the PCIe interface from the host PC, with communication throughput of more than 1.5 GB/s (75% of peak PCIe bandwidth) and reconfiguration of a large accelerator in 20 ms.

关键词： field programmable gate arrays throughput Software Hardware Clocks Registers Data transfer

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High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs

High-level synthesis-based design methodology for Dynamic Po...

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international conference on field programmable logic and applications

作者： Rehan Ahmed Assem A. M. Bsoul Steven J. E. Wilton Peter Hallschmid Richard Klukas The University of British Columbia Canada Blackcomb Design Automation Canada

Static leakage power consumption is critical in modern FPGAs for many applications. Dynamic Power-Gating (DPG), in which parts of the FPGA in-use logic blocks are powered-down at run-time, is a promising technique to reduce the static power. Adoption of such emerging DPG enabled FPGA architectures remains challenging as the current tool-chains to program the FPGA does not support this type of power-gating. Moreover, manually identifying profitable power-gating opportunities in an application requires significant design expertise and is time consuming. In this paper, we propose a high-level synthesis-based design framework that exploits the dynamic power-gating feature of the FPGAs to minimize the static power dissipation. We use this framework on a set of CHStone benchmark suite and demonstrate that power-gating opportunities for hardware accelerators can be identified in an automatic way. Results show that up to 96% reduction in static energy is achieved for individual accelerators using dynamic power-gating technique.

关键词： field programmable gate arrays Benchmark testing Acceleration Design automation Hardware Computer architecture Fabrics

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Incremental distributed trigger insertion for efficient FPGA debug

Incremental distributed trigger insertion for efficient FPGA...

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international conference on field programmable logic and applications

作者： Fatemeh Eslami Steven J.E. Wilton The University of British Columbia Faculty of Medicine Vancouver BC CA

FPGA-based prototyping enables evaluating complex designs directly in hardware, at speeds orders of magnitude faster than simulation. However, this approach suffers from the lack of observability during debugging. To enhance observability, designers insert debug instrumentation; trace buffers are used to record a small subset of data. Since these buffers have limited capacity, trigger circuits are required to start and/or stop recording based on the values of selected signals in the circuit. Although it is possible to insert trigger circuits at compile time, changing the trigger behaviour requires re-compiling the design, increasing the cost of each debug iteration. In this paper, we propose inserting trigger circuits at run-time by distributing trigger logic over spare resources of a fully placed-and-routed design such that its mapping is completely preserved. We also propose CAD optimizations which improve routability of the trigger circuitry, and minimize the impact on circuit delay. We find that using our techniques to implement the trigger logic can be an order of magnitude faster than a full recompilation.

关键词： Routing field programmable gate arrays Delays Benchmark testing Trigger circuits Design automation Random access memory

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An FPGA-optimized architecture of horn and schunck optical flow algorithm for real-time applications

An FPGA-optimized architecture of horn and schunck optical f...

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international conference on field programmable logic and applications

作者： Michael Kunz Alexander Ostrowski Peter Zipf Digital Technology Group University of Kassel Kassel Germany

Optical flow estimation of image sequences is one of the key elements for motion detection. However, processing the optical flow in real-time is still an open task due to its computationally expensive nature. In this paper we present an FPGA-optimized architecture for optical flow estimation based on the algorithm of Horn and Schunck. While existing FPGA-realizations are only partly real-time capable, on a Stratix IV our architecture enables the computation of the optical flow for each pixel of a frame with 640 × 512 pixels at a framerate of 30 fps in iterative and up to 4k resolution (4,096 × 2,304 pixels) at a framerate of 20 fps in full-pipelined form.

关键词： Optical imaging Hardware Computer architecture Kernel Integrated optics Real-time systems Vectors

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A survey of open source processors for FPGAs

A survey of open source processors for FPGAs

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international conference on field programmable logic and applications

作者： Rui Jia Colin Yu Lin Zhenhong Guo Rui Chen Fei Wang Tongqiang Gao Haigang Yang University of Chinese Academy of Sciences Beijing China System on Programmable Chip Research Department Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781479933624

FPGA-based SoCs have been gaining great favors among traditional applications and expanding the application domains to some new areas. Reusing and sharing components is an attractive and pratical methodology for system designers to reduce the design complexity of the SoC architectures. Open source hardware has become an effective method of improving the design productivity. As the core functional component, processors affects the performance of SoC systems. this paper investigates existing open source processors, and gives an overview. From the points of usability and stability, the main features of open source processors are summarized. Following these features, some open source processors with high usability and stability are selected. these open source processors and existing vendor-provided soft processors are implemented on Stratix V and Virtex-7 FPGAs using corresponding EDA tools, Quart us n and ISE. the implementation results are compared and discussed.

关键词： field programmable gate arrays Java Registers Licenses Multicore processing Reduced instruction set computing

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A bit-interleaved embedded hamming scheme to correct single-bit and multi-bit upsets for SRAM-based FPGAs

A bit-interleaved embedded hamming scheme to correct single-...

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international conference on field programmable logic and applications

作者： Shyamsundar Venkataraman Rui Santos Anup Das Akash Kumar Department of Electrical and Computer Engineering National University of Singapore

Single Event Upsets (SEUs) inadvertently change the configuration bits of Static-RAM (SRAM)-based field programmable Gate Arrays (FPGAs), leading to erroneous output until the error has been corrected. Scrubbing using an Error Correction Code (ECC) such as hamming is a popular method to correct such faults. However, current works either require a large external memory to store the ECCs or can at most correct only one error in a frame. this paper proposes a novel bit-interleaved embedded hamming scheme along with scrubbing, to correct single (SBUs) and multi-bit upsets (MBUs) in SRAM-based FPGAs. this scheme does not require an external memory to store the ECCs, as they are embedded within the configuration memory itself. Experiments conducted on various benchmarks show that the proposed scheme can handle multiple errors per frame very well, with an embedding efficiency of over 99.3%.

关键词： field programmable gate arrays Memory management Benchmark testing Error correction Error correction codes Random access memory Runtime

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