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检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

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High-Level FPGA logic Synthesis from. NET Programs for Software Developers the Hastlayer Project 25

High-Level FPGA Logic Synthesis from. NET Programs for Softw...

引用

25th international conference on field programmable logic and applications

作者： Lehoczky, Zoltan Toth, Richard Somogyi, Krisztian Lombiq Technol Ltd Budapest Hungary

ISBN: (纸本)9781467381239

FPGA circuit design, and thus the unique computing power of FPGAs is currently mostly only accessible to experts working in the field. the Hastlayer project aims to give a tool to software developers familiar with the. NET platform to automatically transform performance-critical parts of their programs into seamlessly usable FPGA-implemented hardware, yielding faster program execution and lower power consumption.

关键词： FPGA High-Level Synthesis .NET

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Mapping of P4 Match Action Tables to FPGA 27

Mapping of P4 Match Action Tables to FPGA

引用

27th international conference on field programmable logic and applications (FPL)

作者： Kekely, Michal Korenek, Jan Brno Univ Technol Fac Informat Technol Brno Czech Republic

ISBN: (纸本)9789090304281

Current networks are changing very fast. Network administrators need more flexible and powerful tools to be able to support new protocols or services very fast. the P4 language provides new level of abstraction for flexible packet processing. therefore, we have designed new architecture for memory efficient mapping of P4 match/action tables to FPGA. the architecture is based on DCFL algorithm and is able to balance the processing speed and available memory resources.

关键词： throughput field programmable gate arrays Hardware Memory management Algorithm design and analysis Protocols

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Low-level Loop Analysis and Pipelining of applications mapped to Xilinx FPGAs 29

Low-level Loop Analysis and Pipelining of Applications mappe...

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29th international conference on field-programmable logic and applications (FPL)

作者： Omidian, Hossein Lemieux, Guy G. F. Xilinx Inc San Jose CA 95124 USA Univ British Columbia Vancouver BC Canada

ISBN: (纸本)9781728148847

In this paper we investigate using low-level loop analysis to identify common loop patterns in the netlist generated by the synthesis flow and use loop optimization techniques to increase Fmax of applications implemented on Xilinx FPGAs. Ordinarily, feed-forward paths in the netlist can be easily pipelined. the focus of this study is only sequential loops (with feedback cycles) that are more challenging to optimize. We show that, using low-level loop analysis, we can improve Fmax on average by 57% and achieve an average Fmax of 714MHz across seven industrial designs. Using aggressive loop combining, we also show that we can save 18% area on average while still improving the Fmax by 15% to 41% on four of the seven designs.

关键词： Low-level Loop Analysis FPGA Pipeline Loop Transformation

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Area-optimized Montgomery multiplication on IGLOO 2 FPGAs 27

Area-optimized Montgomery multiplication on IGLOO 2 FPGAs

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27th international conference on field programmable logic and applications (FPL)

作者： Massolino, Pedro Maat C. Batina, Lejla Chaves, Ricardo Mentens, Nele Radboud Univ Nijmegen iCIS Digital Secur Grp Nijmegen Netherlands Univ Lisbon INESC ID IST Lisbon Portugal Katholieke Univ Leuven Imec COSIC Leuven Belgium

ISBN: (纸本)9789090304281

this paper presents the first area-optimized Montgomery modular multiplication module on low-power reconfigurable IGLOO((R)) 2 FPGAs, from Microsemi. In order to obtain a good response time with few resources, the FPGA pipelined Math blocks and the embedded memory blocks are fully leveraged. As a result, 256-bit modular multiplications can be done in 2.33 mu s, at a cost of 505 LUT4 cells, 257 Flip Flops, 1 Math block and 1 64x18 RAM block. If more area resources are considered, a modular multiplication can be performed in 1.25 mu s at a cost of 680 LUT4s, 341 Flip Flops, 2 Math blocks and 2 64x18 RAM blocks. this work is the first fundamental step towards area-efficient public-key cryptography on the Microsemi IGLOO((R)) 2 FPGAs.

关键词： field programmable gate arrays Random access memory Algorithm design and analysis Pipelines Table lookup Galois fields Digital signal processing

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Phase Calibrated Ring Oscillator PUF Design and Implementation on FPGAs 27

Phase Calibrated Ring Oscillator PUF Design and Implementati...

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27th international conference on field programmable logic and applications (FPL)

作者： Yan, Wei Jin, Chenglu Tehranipoor, Fatemeh Chandy, John A. Univ Connecticut Storrs CT 06269 USA

ISBN: (纸本)9789090304281

A ring oscillator physical unclonable function (RO PUF) is an application-constrained hardware security primitive that can be used for authentication and key generation. PUFs depend on variability during the fabrication process to produce random outputs that are nevertheless stable across multiple measurements. Unfortunately, RO PUFs are known to be unstable especially when implemented on an field programmable Gate Array (FPGA). In this work, we comprehensively evaluate the RO PUF's stability on FPGAs, and we propose a phase calibration process to improve the stability of RO PUFs. the results show that the bit errors in our PUFs are reduced to less than 1%.

关键词： Physical Unclonable Function Ring Oscillator Phase Calibration field programmable Gate Array

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A Technology Mapper for Depth-Constrained FPGA logic Cells 25

A Technology Mapper for Depth-Constrained FPGA Logic Cells

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25th international conference on field programmable logic and applications

作者： Jiang, Zhenghong Zgheib, Grace Lin, Colin Yu Novo, David Huang, Zhihong Yang, Liqun Yang, Haigang Ienne, Paolo Chinese Acad Sci Inst Elect Syst Programmable Chip Res Dept Beijing Peoples R China Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland

ISBN: (纸本)9781467381239

In the last decade, progress in logic synthesis has brought about new advantageous circuit representations. these representations, such as And-Inverter Graphs in the ubiquitous open-source synthesizer ABC, have inspired new designs of field programmable Gate Arrays (FPGAs), which, instead of using Look-Up Tables (LUTs), mimic the topology of the circuit representation in the basic logic cells. More recent examples are Majority-Inverter Graphs, another uniform representation which has triggered considerable interest in synthesis and which naturally suggests new logic cells. Yet, in this paper we observe how naively adapting technology mapping solutions for classic LUT-based FPGAs to these new architectures incurs severe shortcomings. the key issue is that LUTs are inherently input-constrained (the logic function they implement is irrelevant) and have generally a single output;on the other hand, logic cells made of uniform networks of some fundamental logic function (e.g., And-Invert) are constrained in terms of logic depth and multiple outputs are an integral feature. We introduce novel and effective solutions to address these differences;the result is a highly versatile mapper-thus enabling further research in these new architectures-with a significantly better performance than what is described in literature for one such architecture. Specifically, when we compare with the state of the art on one sample architecture, we obtain a significant decrease in area (on average 18% over several benchmarks) while also improving slightly the critical path (a reduction of 3%).

关键词： field programmable gate arrays (FPGA)

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High-Speed Chromatic Dispersion Compensation Filtering in FPGAs for Coherent Optical Communication 30

High-Speed Chromatic Dispersion Compensation Filtering in FP...

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30th international conference on field-programmable logic and applications (FPL)

作者： Bae, Cheolyong Gustafsson, Oscar Linkoping Univ Dept Elect Engn Linkoping Sweden

ISBN: (纸本)9781728199023

Chromatic dispersion is one of the error sources limiting the transmission capacity in coherent optical communication that can be mitigated with digital signal processing. In this paper, the current status and plans of implementation of chromatic dispersion compensation (CDC) filters on FPGAs are discussed. As these high-speed filters are most efficiently implemented in the frequency-domain, different approaches for high-speed FFT-based architectures are considered and preliminary results of fully parallel FFT implementation by utilizing FPGA hardware features are presented.

关键词： Chromatic dispersion compensation (CDC) fast Fourier transform (FFT) field-programmable gate arrays (FPGAs)

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Characterizing Latency Overheads in the Deployment of FPGA Accelerators 30

Characterizing Latency Overheads in the Deployment of FPGA A...

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30th international conference on field-programmable logic and applications (FPL)

作者： Cooke, Ryan A. Fahmy, Suhaib A. Univ Warwick Sch Engn Coventry W Midlands England

ISBN: (纸本)9781728199023

FPGA hardware accelerators have recently enjoyed significant attention as platforms for further accelerating computation in the datacenter but they potentially add additional layers of hardware and software interfacing that can further increase communication latency. In this paper, we characterize these overheads for streaming applications where latency can be an important consideration. We examine the latency and throughput characteristics of traditional server-based PCIe connected accelerators, and the more recent approach of network attached FPGA accelerators. We additionally quantify the additional overhead introduced by virtualising accelerators on FPGAs.

关键词： field programmable gate arrays (FPGA)

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Placing Partially Reconfigurable Stream Processing applications on FPGAs 25

Placing Partially Reconfigurable Stream Processing Applicati...

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25th international conference on field programmable logic and applications

作者： Grigore, Nicolae Bogdan Koch, Dirk Univ Manchester Manchester M13 9PL Lancs England

ISBN: (纸本)9781467381239

Finding placement locations for modules on an FPGA in a limited amount of time is a crucial task that determines the efficiency of a dynamic partially reconfigurable system. In this work, we will define a placement method based on transforming the inherent two dimensional (2D) structure of the FPGA into a one dimensional string and employing string matching. Moreover, our model is suited to compute a module placement over multiple chained reconfigurable regions. Our algorithm is based on a hybrid approach consisting of an offline precompute phase at design-time which in turn is used to speed-up module placement at run-time.

关键词： field programmable gate arrays configurability placement Runtime design year

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FPGA-based All-digital Transmitters 25

FPGA-based All-digital Transmitters

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25th international conference on field programmable logic and applications

作者： Cordeiro, R. F. Oliveira, Arnaldo S. R. Vieira, Jose Univ Aveiro DETI Inst Telecomunicaes Aveiro Portugal

ISBN: (纸本)9781467381239

this paper presents the architecture and implementation of an FPGA-based all digital transmitter for wireless radio communications. these transmitters allow a greater degree of flexibility for the carrier frequency, signal bandwidth and the use of simultaneous multiple-standards. Latest advances in the state-of-the-art in this emerging area are presented as well as the remaining issues to he solved and the proposed architecture to address some them.

关键词： Flexibility Transmitters field programmable gate arrays Building construction ARCHITECTURE Radiocommunication signal bandwidth

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