A novel routing fabric is introduced that offers high flexibility at significant lower silicon cost compared to routing fabrics currently incorporated in many fieldprogrammable Gate Array (FPGA) devices, IP cores, an...
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ISBN:
(纸本)9781424410590
A novel routing fabric is introduced that offers high flexibility at significant lower silicon cost compared to routing fabrics currently incorporated in many fieldprogrammable Gate Array (FPGA) devices, IP cores, and IP-core wrappers. the novel fabric is entirely constructed from multiplexers and unidirectional point-to-point connections, controlled by configuration bits, and proves very efficient when mapping applications. For a fabric connecting 4-input Look-Up-Tables, area savings of 60% are demonstrated when routing applications from the MCNC benchmark set.
this paper presents a field-programmable gate array (FPGA) logic synthesis technique based upon Boolean satisfiability. this paper shows how to map any Boolean function into an arbitrary programmablelogic block (PLB)...
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this paper presents a field-programmable gate array (FPGA) logic synthesis technique based upon Boolean satisfiability. this paper shows how to map any Boolean function into an arbitrary programmablelogic block (PLB) architecture without any custom decomposition techniques. the authors illustrate several useful applications of this technique by showing how this technique can be used for architecture evaluation and area optimization. When evaluating the FPGA architecture, the authors focus on the basic building block of the FPGA, which they refer to as PLB. In order to illustrate the flexibility of their evaluation framework, several unrelated PLB architectures are evaluated in an automated fashion. Furthermore, the authors show that using their technique is able to reduce FPGA resource usage by 27% on average in common subcircuits found in digital design.
this paper describes an execution cache that uses process migration between hardware and software contexts by way of run-time reconfiguration (RTR) of fieldprogrammable Gate Arrays (FPGAs). the feasibility of such a ...
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ISBN:
(纸本)9781424410590
this paper describes an execution cache that uses process migration between hardware and software contexts by way of run-time reconfiguration (RTR) of fieldprogrammable Gate Arrays (FPGAs). the feasibility of such a system is demonstrated using existing FPGAs by accelerating a cycle-based simulation of a Register Transfer Level (RTL) design description. through the use of a common instruction set, each simulation process may be run in a software Virtual Machine (VM) or in a hardware Real Machine (RM). the implementation provides data for an empirical model used to examine the behavior of unimplemented parts of the system.
FPGA is currently a very important design technology to implement electronic systems due to its high logic density, its fast time-to-market and its low cost. But in order to provide high logic density FPGA devices are...
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ISBN:
(纸本)9781424410590
FPGA is currently a very important design technology to implement electronic systems due to its high logic density, its fast time-to-market and its low cost. But in order to provide high logic density FPGA devices are fabricated with nanometer CMOS technology that is becoming susceptible to radiation-induced soft errors. Among these errors, single-event transients (SETs) are those that are induced in the user's programmablelogic. this paper presents a new fast adder, called RIC (Re-computing the Inverse Carry-in) and shows how this new adder architecture may be used to build SET-tolerant fast adders. Results considering FPGA-based implementation are presented.
this paper presents an architecture for the computation of the atan(Y/X) operation suitable for broadband communication applications where a throughput of 20 MHz is required. the architecture is based on LUT methods a...
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ISBN:
(纸本)9781424410590
this paper presents an architecture for the computation of the atan(Y/X) operation suitable for broadband communication applications where a throughput of 20 MHz is required. the architecture is based on LUT methods and achieves lower power consumption with respect to an atan(Y/X) operator based on CORDIC algorithm with a lower latency. the proposed architecture can compute the atan(Y/X) with a latency of two clock cycles and its power consumption is 49% lower than a CORDIC withthe same latency.
this paper discusses the need for new high-speed hardware architectures for future networks and in particular the need for high speed, high capacity shared buffer designs. An implementation of such a buffer using FPGA...
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ISBN:
(纸本)9781424410590
this paper discusses the need for new high-speed hardware architectures for future networks and in particular the need for high speed, high capacity shared buffer designs. An implementation of such a buffer using FPGA technology utilizing RLDRAM II is presented. the architecture that has been derived and implemented operated at 12.8Gbps and is scalable up to 20Gbps.
this paper develops a formal model of process migration that describes pro.-rams, processes, and the migration of those processes within a migration realm. A migration realm is a group of processors modeled as finite ...
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ISBN:
(纸本)9781424410590
this paper develops a formal model of process migration that describes pro.-rams, processes, and the migration of those processes within a migration realm. A migration realm is a group of processors modeled as finite state machines. the model is motivated by a migration application between software and fieldprogrammable Gate Array (FPGA) hardware, and the theorems of the model guide the use of FPGA resources while guaranteeing complete and correct execution of a process. By defining different types of migration realms this paper also develops a migration realm taxonomy.
this paper presents and discusses implementation of a barotropic operator used in ocean model simulation called Parallel Ocean Program (POP) using SRC-6 MAP. While a lot of high-end reconfigurable machines on which us...
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ISBN:
(纸本)9781424410590
this paper presents and discusses implementation of a barotropic operator used in ocean model simulation called Parallel Ocean Program (POP) using SRC-6 MAP. While a lot of high-end reconfigurable machines on which users can implement applications with a programming language are now available, enough implementation experience has not been accumulated for practical applications. In this paper, several implementation techniques accompanied by modification on original application source code are empirically evaluated and analyzed. the results show that appropriate use of internal memory and streaming DMA make 100 MHz FPGAs achieve comparative performance with GHz processors by using 100 MHz FPGAs.
We demonstrate a hybrid reconfigurable cluster-on-chip architecture with a cross-platform Message Passing Interface (MPI), a cross-platform parallel image processing library and a sample application. We describe the s...
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ISBN:
(纸本)9781424410590
We demonstrate a hybrid reconfigurable cluster-on-chip architecture with a cross-platform Message Passing Interface (MPI), a cross-platform parallel image processing library and a sample application. We describe the system, network architecture, MPI library and the parallel image processing library implementations. We validate the performance, scalability and suitability of MPI as a software interface to enable cross-platform application parallelism on reconfigurable hybrid cluster-on-chip systems and desktop cluster systems. the presented results are promising, showing the suitability, scalability and performance of parallelisation of image processing algorithms with a cross-platform MPI implementation.
Reconfiaurable logic Devices are classified as the fine-grained or coarse-rained type on the basis of their basic logic cell architecture. In general, each architecture has its own merit;therefore, it is difficult to ...
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ISBN:
(纸本)9781424410590
Reconfiaurable logic Devices are classified as the fine-grained or coarse-rained type on the basis of their basic logic cell architecture. In general, each architecture has its own merit;therefore, it is difficult to achieve a balance between the operation speed and implementation area in various applications. In this paper, we propose a Variable Grain logic Cell (VGLC) architecture, which consists of a 4-bit ripple carry adder with configuration memory bits and also develop technology mapping tool. Its key feature is the variable granularity being a trade-off between coarse-grained and fine-grained types required for the implementation arithmetic and random logic, respectively. As a result, critical path delay, and number of configuration memory bits are reduced by 49.7%, and 48.5%, respectively, in the benchmark circuits.
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