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17th international conference on field programmable logic and applications

作者： Suh, Taeweon Lu, Shih-Lien Lee, Hsien-Hsin S. Intel Corp Platform Validat Architecture Santa Clara CA 95051 USA Intel Labs Microarchitecture Res Hillsboro OR 97124 USA Georgia Inst Elect & Comp Engn Atlanta GA 30332 USA

ISBN: (纸本)9781424410590

Recently, there is a surge of interests in using FPGAs for computer architecture research including applications from emulating and analyzing a new platform to accelerating microarchitecural simulation speed for design space exploration. this paper proposes and demonstrates a novel usage of FPGAs for measuring the efficiency of coherent traffic of an actual computer system. Our approach employs an FPGA acting as a bus agent, interacting with a real CPU in a dual processor system to measure the intrinsic delay of coherence traffic. this technique eliminates non-deterministic factors in the measurement, such as the arbitration delay and stall in the pipelined bus. It completely isolates the impact of pure coherence traffic delay on system performance while executing workloads natively. Our experiments show that the overall execution time of the benchmark programs on a system with coherence traffic was actually increased over one without coherent traffic. It indicates that cache-to-cache transfers are less efficient in an Intel-based server system, and there exists room for further improvement such as the inclusion of the O state and cache line buffers in the memory controller.

关键词： field programmable gate arrays (FPGA)

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Domain-specific hybrid FPGA: Architecture and floating point applications

Domain-specific hybrid FPGA: Architecture and floating point...

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17th international conference on field programmable logic and applications

作者： Ho, Chun Hok Yu, Chi Wai Leong, Philip H. W. Luk, Wayne Wilton, Steven J. E. Imperial Coll London Dept Comp London England Chinese Univ Hong Kong Dept Comp Sci & Engn Hong Kong Peoples R China Univ British Columbia Dept Elect & Comp Engn Vancouver BC V5Z 1M9 Canada

ISBN: (纸本)9781424410590

this paper presents a novel architecture for domain-specific FPGA devices. this architecture can be optimised for both speed and density by exploiting domain-specific information to produce efficient reconfigurable logic with multiple granularity. In the reconfigurable logic, general-purpose fine-grained units are used for implementing control logic and bit-oriented operations, while domain-specific coarse-grained units and heterogeneous blocks are used for implementing datapaths;the precise amount of each type of resources can be customised to suit specific application domains. Issues and challenges associated with the design flow and the architecture modelling are addressed. Examples of the proposed architecture for speeding up floating point applications are illustrated. Current results indicate that the proposed architecture can achieve 2.5 times improvement in speed and IS times reduction in area on average, when compared with traditional FPGA devices on selected floating point benchmark circuits.

关键词： Reconfigurable architectures

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Efficient external memory interface for multi-processor platforms realized on FPGA chips

Efficient external memory interface for multi-processor plat...

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17th international conference on field programmable logic and applications

作者： Nikolov, Hristo Stefanov, Todor Deprettere, Ed Leiden Univ LIACS NL-2300 RA Leiden Netherlands

ISBN: (纸本)9781424410590

the complexity of today's embedded applications requires modern high-performance embedded System-on-Chip (SoC) platforms to be multiprocessor architectures. Advances in FPGA technology make the implementation of such architectures in a single chip (MP-SoC) feasible and very appealing. In recent years, the FPGA vendors integrated enormous amount of hardware resources in their FPGAs allowing larger and more complex MPSoCs to be built in their FPGA fabric. the main limitation on the size of an MPSoC that can be built in a single FPGA appears to be the amount Of on-chip memory. To relax this limitation, the usage of external (off-chip) memory has to be considered. the state-of-the-art development tools support off-chip memory for (multi-master) shared bus architectures with arbitration of the memory accesses. Such architectures might be efficient for single processor systems however for multiprocessor systems the shared bus concept significantly limits the systems performance even if a DMA mechanism is used. In this paper we present our approach and interface when using an external memory for inter-processor data communication in multiprocessor platforms. We propose a hierarchical memory system with a programmable controller to transfer data between external and on-chip memories using a DMA mechanism. Our approach does not require arbitration which results in better overall performance. Results demonstrating the effectiveness of the proposed hierarchical memory system are presented as well.

关键词： field programmable gate arrays (FPGA)

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the design of multitasking based applications on reconfigurable instruction cell based architectures

The design of multitasking based applications on reconfigura...

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17th international conference on field programmable logic and applications

作者： Wei, Han Nousias, Ioannis Muir, Mark Arslan, Tughrul Erdogan, Andahmet T. Univ Edinburgh Edinburgh EH8 9YL Midlothian Scotland

ISBN: (纸本)9781424410590

this paper presents a new direct implementation of a popular RTOS with an associated application - the WiMAX physical layer - on reconfigurable computing architectures. A novel coarse-gained reconfigurable instruction cell based architecture is chosen as the target architecture. Firstly an RTOS - Micro C/0S-II - was ported to the target architecture, and then the WiMAX physical layer program was partitioned into multiple OS tasks which communicate with each other through the synchronization approaches provided by this RTOS. the WiMAX physical layer program has been also implemented on the ARM7TDMI processor. the results show that the performance of the target architecture is much better than the ARM7TDMI, and not limited by the bottleneck of memory latency.

关键词： Reconfigurable architectures

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Circuit switched run-time adaptive network-on-chip for image processing applications

Circuit switched run-time adaptive network-on-chip for image...

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17th international conference on field programmable logic and applications

作者： Braun, Lars Huebner, Michael Becker, Juergen Perschke, thomas Schatz, Volker Bach, Stefan Univ Karlsruhe ITIV Engesserstr 5 D-76131 Karlsruhe Germany Forschungs Inst Optron & Mustererkennung D-76275 Ettlingen Germany

ISBN: (纸本)9781424410590

Since the 1990s reusable functional blocks, well known as IP-Cores, have been integrated on one silicon die. these Systems-on-Chip (SoC) used a bus-based system for inter-module communication. Technology, performance and flexibility issues require the introduction of a novel communication system called Network-on-Chip (NoC). A-round 1999 this method was introduced and since then has been investigated by several research groups with the aim to connect different EP-Cores through an effective, flexible and scalable communication network. Exploiting the flexibility of FPGAs, the run-time adaptivity through run-time reconfiguration, opens a new area of research by considering dynamic and partial reconfiguration. Since software parts of an electronic system can also be included into reconfigurable hardware by integration of IP-based microcontrollers, the reconfigurable architecture provides a flexible, multi-adaptive heterogeneous platform for HW / SW Co-designs. this paper presents an approach for exploiting dynamic and partial reconfiguration with Xilinx Virtex-II FPGAs for an adaptive circuit switched Network-on-Chip and the related techniques for adapting the system during run-time to the requirements of the presented image processing application.

关键词： Network-on-chip

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Accelerating a medical 3D brain MRI analysis algorithm using a high-performance reconfigurable computer

Accelerating a medical 3D brain MRI analysis algorithm using...

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17th international conference on field programmable logic and applications

作者： Koo, Jahyun J. Evans, Alan C. Gross, Warren J. McGill Univ Dept Elect & Comp Engn Montreal PQ Canada Montreal Neurol Inst McConnell Brain Imaging Ctr Montreal PQ Canada

ISBN: (纸本)9781424410590

Many automatic algorithms have been proposed for analyzing magnetic resonance imaging (MRI) data sets. these algorithms allow clinical researchers to generate quantitative data analyses with consistently accurate results. With the increasingly large data sets being used in brain mapping, there has been a significant rise in the need for methods to accelerate these algorithms, as their computation time can consume many hours. this paper presents the results from a recent study on implementing such quantitative analysis algorithms on High-Performance Reconfigurable Computers (HPRCs). A brain tissue classification algorithm for MRI, the Partial Volume Estimation (PVE), is implemented on an SGI RASC RC100 system using the Mitrion-C High-Level Language (HLL). the CPU-based PVE algorithm is profiled and computationally intensive floating-point functions are implemented on FPGA-accelerators. the images resulting from the FPGA-based algorithm are compared to those generated by the CPU-based algorithm for verification. the Similarity Indexes (SI) for pure tissues are calculated to measure the accuracy of the images resulting from the FPGA-based implementation. the portion of the PVE algorithm that was implemented on hardware achieved a 11 x performance improvement over the CPU-based implementation. the overall performance improvement of the FPGA-accelerated PVE algorithm was 3.5 x with four FPGAs.

关键词： field programmable gate arrays (FPGA)

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Dynamic partial FPGA reconfiguration in a prototype microprocessor system

Dynamic partial FPGA reconfiguration in a prototype micropro...

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17th international conference on field programmable logic and applications

作者： Schleupen, Kai Lekuch, Scott Mannion, Ryan Guo, Zhi Najjar, Walid Vahid, Frank IBM System and Technology Group Department of Computer Science and Engineering University of California Riverside United States Brocade Communications System

ISBN: (纸本)9781424410590

Modem FPGAs' parallel computing capability and their ability to be reconfigured make them an ideal platform to build accelerators for supercomputing systems. As a multicore processor, the recently announced Cell Broadband EngineTM1 offers tremendous computing power. In this paper, we introduce a prototype system that combines these two types of computing devices together in a reconfigurable blade and we describe its architecture, memory system and abundant interfaces. On the reconfigurable blade it is desirable that the FPGA devices can be partially reconfigured at run-time. this paper presents the dynamic partial reconfiguration (DPR) technique and its design flow for the reconfigurable blade. We report our experimental results of the blade doing partial reconfiguration. DPR allows the reconfigurable blade to be a powerful, run-time changeable computing engine. A sample application is presented that was both simulated for the Cell processor and dynamically loaded to run on the FPGA.

关键词： field programmable gate arrays (FPGA)

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Statistical placement for FPGAs considering process variation

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IET COMPUTERS AND DIGITAL TECHNIQUES 2007年第4期1卷 267-275页

作者： Lin, Y. Hutton, M. He, L. Univ Calif Los Angeles Dept Elect Engn Los Angeles CA 90095 USA Altera Corp San Jose CA 95134 USA

Process variations affecting timing and power is an important issue for modem integrated circuits in nanometre technologies. field programmable gate arrays (FPGA) are similar to application-specific integrated circuit (ASIC) in their susceptibility to these issues, but face unique challenges in that critical paths are unknown at test time. the first in-depth study on applying statistical timing analysis with cross-chip and on-chip variations to speed-binning and guard-banding in FPGAs has been presented. Considering the uniqueness of re-programmability in FPGAs, the effects of timing-model with guard-banding and speed-binning on statistical performance and timing yield are quantified. A new variation aware statistical placement, which is the first statistical algorithm for FPGA layout and achieves a yield loss of 29.7% of the original yield loss with guard-banding and a yield loss of 4% of the original one with speed-binning for Microelectronics Center of North Carolina (MCNC) and Quartus University Interface Program (QUIP) designs, has also been developed.

关键词： integrated circuit layout statistical analysis statistical timing analysis logic design on-chip variations statistical placement process variation cross-chip speed-binning modern integrated circuits nanometre technologies timing guard-banding FPGA layout application-specific integrated circuit field programmable gate arrays

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Implementation of a virtual internal configuration access port (JCAP) for enabling partial self-reconfiguration on Xilinx Spartan III FPGAs

Implementation of a virtual internal configuration access po...

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17th international conference on field programmable logic and applications

作者： Paulsson, K. Huebner, M. Auer, G. Dreschmann, M. Chen, L. Becker, J. Univ Karlsruhe Inst Informat Proc Technol Karlsruhe Germany

ISBN: (纸本)9781424410590

the exploitation of dynamic and partial hardware reconfiguration on FPGAs is currently being investigated in various research projects, dealing with systems for space applications to automotive and masurement applications. Despite challanges such as a complicated design flow, dynamic reconfigurable systems offer advantages in terms of flexibility and performance. Unfortunately only few kinds of commercial architectures support dynamic and partial reconfiguration, which has lead to Virtex II/IV being main target architectures for this kind of systems. Additionally, the Xilinx Spartan III architecture is dynamically and partially reconfigurable with some limitations, one of them being the lack of an internal configuration port. the Virtex II/IV and V architectures all include the ICAP port, which allows a system to reconfigure itself during run-time without additional external components. Until now, this was not possible on the Spartan III architecture. this paper presents the implementation of a virtual internal configuration port for the Spartan III family of FPGAs. the configuration port was implemented for a hardware reconfigurable measurement system, which is implemented on a Spartan III FPGA due to its cost- and power optimized characteristics.

关键词： field programmable gate arrays (FPGA)

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A self-reconfigurable implementation of the JPEG encoder

A self-reconfigurable implementation of the JPEG encoder

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18th IEEE international conference on Application-Specific Systems, Architectures and Processors

作者： Tumeo, Antonino Monchiero, Matteo Palermo, Gianluca Ferrandi, Fabrizio Sciuto, Donatella Politecn Milan Dipartimento Elettr & Informat I-20133 Milan Italy

ISBN: (纸本)9781424410262

Dynamic reconfiguration allows to selectively substitute blocks of logic at run-time in order to improve the area efficiency of a FPGA design. this paper presents the design of a JPEG Encoder which exploits this feature. We propose a mixed HW/SW architecture, where most compute-intensive components of the application are mapped to application-specific HW cores. these cores dynamically alternate on the FPGA. Our purpose is to describe a real-world application of reconfigurable computing, illustrating how this approach allows for saving area with negligible performance overhead. We built a fully-working prototype, which demonstrates that the reconfigurable JPEG encoder achieves 29.6% area saving;1.5% performance loss, and negligible power overhead with respect to a solution which uses statically mapped HW cores.

关键词： field programmable gate arrays (FPGA)

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