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IEEE NPSS conference on Real Time

作者： Alexander Mann Igor Konorov Stephan Paul Physik-Department E18 Technische Universität München Garching Germany

A data acquisition system based on sampling analog to digital converters (ADCs) and data processing in field programmable gate arrays (FPGAs) is presented. Up to 32 ADC channels are combined with reconflgurable logic on a small mezzanine form factor card to get a handy module for analog data acquisition. this module can then be mounted either on a dedicated detector frontend or included in an Advanced Telecom Computing Architecture (ATCA) crate system. For on-detector usage the system provides several features for fail safe and also fail tolerant operation and data readout. this opens applications in high energy physics detectors with difficult access schemes to the electronic part. the crate system offers on the other hand a high channel density with moderate channel costs. Additionally, the ATCA standard provides enough data bandwidth for online data processing within the crate system. Due to the unified interface of the ADC mezzanine cards, the system cost can be further reduced by an easy up- or downgrade of the ADC sampling frequency or the channel count by exchanging just the mezzanine card and thus maintaining the whole surrounding infrastructure. this enables to serve different detector requirements with a limited number of different mezzanine card types and eases also further enhancements with new upcoming ADC or FPGA devices.

关键词： Sampling methods field programmable gate arrays Detectors Data acquisition Data processing Costs Analog-digital conversion field programmable analog arrays programmable logic arrays Telecommunication computing

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High level area estimation of custom instructions for FPGA-based reconfigurable processors

High level area estimation of custom instructions for FPGA-b...

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international conference on Information, Communications and Signal Processing

作者： Siew-Kei Lam Wen Li thambipillai Srikanthan Centre for High Performance Embedded Systems Nanyang Technological University Singapore School of Software Peking University China

ISBN: (纸本)9781424409822

Reconfigurable processors provide an attractive means to meet the constraints of embedded devices due to their instruction set extension capabilities. We propose a novel technique to estimate the area utilization of LUT (Look-Up Table) based FPGAs (field programmable Gate Arrays) for custom instruction realizations. the technique contributes to rapid design exploration by computing the hardware area utilization of custom instructions without actual hardware synthesis. the proposed area estimation technique is achieved in two stages. In the first stage, a set of partitions are obtained from the custom instruction data-paths based on some rule-sets that satisfy the FPGA constraints. Each partition represents a unique LUT configuration that can be implemented on a FPGA logic element. In the second stage, the partitions are combined to maximize the area efficiency on FPGA. We show that the proposed technique can overcome the limitation of existing datapath merging methods that are based on maximizing resource sharing. Experimental results show that an average of 12 unique LUT configurations (about 22% of the logic elements in the smallest Xilinx Virtex FPGA) can sufficiently cater to seven applications from the MiBench benchmark suite.

关键词： field programmable gate arrays Table lookup Hardware Embedded system Merging System-on-a-chip Resource management Application software Reconfigurable logic Time to market

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Optimization of Moore FSM on FPGA

Optimization of Moore FSM on FPGA

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international conference on CAD Systems in Microelectronics (CADSM)

作者： Larysa Titarienko Marek Wegrzyn S. Cololo Institute of Computer Engineering and Electronics University of Zielona Góra Zielona Poland

A new method of Moore FSM circuit optimization is proposed, which is based on generation of both codes of the states and codes of the classes of pseudoequivalent states of FSM. the presented method permits to encode the states of FSM in such manner that some microoperations can be implemented using single LUT element. Other microoperations should be implemented using dedicated memory blocks. Minimization of the system of excitation functions is reached thanks to separate source of the codes of the classes of pseudoequivalent states. Such approach allows minimizing hardware amount in the circuit of FSM. the conditions for such optimization are shown. An example of proposed method's application is given.

关键词： field programmable gate arrays Table lookup System-on-a-chip Roentgenium logic arrays Digital multimedia broadcasting Optimization methods Circuit optimization Minimization Hardware

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Hardware libraries: An architecture for economic acceleration in soft multi-core environments

Hardware libraries: An architecture for economic acceleratio...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： David Meisner Sherief Reda Division of Engineering Brown University Providence USA

ISBN: (纸本)9781424412570;1424412587

In single processor architectures, computationally- intensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to achieve a significant speedup over software. the increased design constraints from power density and signal delay have shifted processor architectures in general towards multi-core designs. the migration to multi-core designs introduces the possibility of sharing hardware accelerators between cores. In this paper, we propose the concept of a hardware library, which is a pool of accelerated functions that are accessible by multiple cores. We find that sharing provides significant reductions in the area, logic usage and leakage power required for hardware acceleration. Contention for these units may exist in certain cases; however, the savings in terms of chip area are more appealing to many applications, particularly the embedded domain. We study the performance implications for our proposal using various multi-core arrangements, with actual implementations in FPGA fabrics. FPGAs are particularly appealing due to their cost effectiveness and the attained area savings enable designers to easily add functionality without significant chip revision. Our results show that is possible to save up to 37% of a chip's available logic and interconnect resources at a negligible impact (< 3%) to the performance.

关键词： Libraries Hardware Software Acceleration field programmable gate arrays Computer architecture Silicon

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FPGA programmable logic block evaluation using quantified Boolean satisfiability

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 2006年第3期153卷 165-172页

作者： Ling, A. C. Singh, D. P. Brown, S. D. Univ Toronto Toronto ON M5S 3G4 Canada Altera Toronto Technol Ctr Toronto ON M5S 1S4 Canada

A novel field programmable gate array (FPGA) logic synthesis technique that determines if a logic function can be implemented in a given programmable circuit is presented, and how this problem can be formalised and solved using quantified Boolean satisfiability is described. this technique is general enough to be applied to any type of logic function and programmable circuit;thus, it has many applications to FPGAs. the application demonstrated is the FPGA programmable logic block evaluation and the results show that this tool allows radical new features of FPGA logic blocks to be evaluated in a rigorous scientific way.

关键词： logic circuits Formal logic logic synthesis technique field programmable gate arrays logic design Boolean functions logic function Boolean satisfiability Digital circuit design, modelling and testing logic and switching circuits logic design methods field programmable gate array programmable circuit programmable logic block evaluation computability

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Configware design space exploration using rewriting logic

Configware design space exploration using rewriting logic

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16th international conference on field programmable logic and applications

作者： Morra, C. Univ Karlsruhe ITIV Karlsruhe Germany

No abstract available

ISBN: (纸本)9781424403127

No abstract available

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Defect tolerance in multiple-FPGA systems

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 2006年第3期153卷 139-145页

作者： Hyder, Z. Wawrzynek, J. Univ Calif Berkeley Berkeley CA 94720 USA

SRAM-based field programmable gate arrays (FPGAs) have an inherent capacity for defect tolerance. A simple scheme that exploits this potential in multiple-FPGA systems is prod posed. the symmetry of the system is exploited to yield a large number of possible mappings of bitstreams on FPGAs, which results in a high probability that at least one functional mapping exists. It is shown that the behaviour of a system built using a large number of defective FPGAs approaches that of the ideal defect-free system. Various interconnection topologies such as the tree, the crossbar and a hybrid form are compared.

关键词： multiple FPGA system SRAM chips field programmable gate arrays defect tolerance functional bitstream mapping interconnection topology Memory circuits SRAM defect free system logic and switching circuits defective FPGA static random access memory field programmable gate array Performance evaluation and testing logic circuits fault tolerant computing Semiconductor storage

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Intelligent parking system design using FPGA

Intelligent parking system design using FPGA

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16th international conference on field programmable logic and applications

作者： Song, Insop Gowan, Keith Nery, Jason Han, Henrick Shegn, Tong Li, Howard Karray, Fakhreddine Univ Waterloo Dept Elect & Comp 200 Univ Ave W Waterloo ON N2L 3G1 Canada

ISBN: (纸本)9781424403127

In this research, we introduce FPGA based fuzzy logic controller (FLC). the benefit of using FPGA based FLC compare to software FLC is that the computation time reduction. Using this FLC, we design automated car back parallel parking system also with complete FPGA based controller. We build a small-scaled robot car and test on a real environment with VHDL code for wall following and parking. this paper describes the background of fuzzy logic system, the design of fuzzy logic system with FPGA and the experimental results.

关键词： field programmable gate arrays (FPGA)

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Accelerating molecular dynamics simulations with configurable circuits

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 2006年第3期153卷 189-195页

作者： Gu, Y. VanCourt, T. Herbordt, M. C. Boston Univ Dept Elect & Comp Engn Boston MA 02215 USA

Molecular dynamics (MD) is of central importance to computational chemistry. Here the authors show that MD can be implemented efficiently on a commercial off-the-shelf (COTS) field programmable gate array (FPGA) board, and that speed-ups from 31 x to 88 x over a PC implementation can be obtained. Although the extent of speed-up depends on the stability required, 46x can be obtained with virtually no detriment, and the upper end of the range is apparently viable in many cases. the authors sketch the FPGA implementations and describe the effects of precision on the trade-off between the performance and quality of the MD simulation.

关键词： FPGA field programmable gate array board digital simulation Physics and chemistry computing field programmable gate arrays configurable circuits biology computing Biology and medical computing computational chemistry logic and switching circuits logic circuits molecular dynamics method chemistry computing molecular dynamics simulations

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Rapid system-on-a-programmable-chip development and hardware acceleration of ANSI C functions

Rapid system-on-a-programmable-chip development and hardware...

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16th international conference on field programmable logic and applications

作者： Lau, David J. Pritchard, Orion Altera Corp Santa Cruz Technol Ctr 110 Cooper St Santa Cruz CA 95060 USA

ISBN: (纸本)9781424403127

this tutorial explores the use of the System on a programmable Chip as an ideal platform for rapid development of embedded solutions. Many sophisticated tools exist that facilitate rapid development of embedded systems on a chip. As an example, we discuss a suite of three tightly-coupled embedded systems development tools from Altera, including: (1) hardware system generation and integration, (2) embedded software development, and (3) automatic hardware acceleration of ANSIASO-spec C functions.

关键词： Embedded systems

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