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检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

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FPGA-ORIENTED SECURE DATA PAth DESIGN: IMPLEMENTATION OF A PUBLIC KEY COPROCESSOR

<bold>FPGA-ORIENTED SECURE DATA PATH DESIGN: IMPLEMENTATION ...

引用

16th international conference on field programmable logic and applications

作者： Mentens, Nele Sakiyama, Kazuo Batina, Lejla Verbauwhede, Ingrid Preneel, Bart Katholieke Univ Leuven COSIC ESAT SCD Kasteel Pk Arenberg 10 B-3001 Heverlee Belgium

ISBN: (纸本)9781424403127

this paper introduces a secure FPGA implementation of a coprocessor for public key cryptography. It supports Elliptic Curve Cryptography (ECC) as well as the older RSA standard. When choosing adequate key lengths, RSA and ECC are assumed to be secure from an algorithmic point of view. On the other hand, an implementation of these algorithms should also guarantee side-channel security. this feature does not only cause an inevitable performance degradation, but also an area increase. We overcome these drawbacks by fitting the public key architecture and algorithms into a coprocessor that optimally exploites the dedicated features on a Spartan XC3S4000. Although this is a very low-cost FPGA, the performance results of our implementation meet the requirements of a broad range of high-end applications.

关键词： field programmable gate arrays (FPGA)

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FPGA based acceleration of the linpack benchmark: A high level code transformation approach

FPGA based acceleration of the linpack benchmark: A high lev...

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16th international conference on field programmable logic and applications

作者： Turkington, Kieron Masselos, Konstantinos Constantinides, George A. Leong, Philip Univ London Imperial Coll Dept Elect & Elect Engn London England Univ London Imperial Coll Dept Comp London England

ISBN: (纸本)9781424403127

Due to their increasing resource densities, field programmable gate arrays (FPGAs) have become capable of efficiently implementing large scale scientific applications involving floating point computations. In this paper FPGAs are compared to a high end microprocessor with respect to sustained performance for a popular floating point CPU performance benchmark, namely LINPACK 1000. A set of translation and optimization steps have been applied to transform a sequential C description of the LINPACK benchmark, based on a monolithic memory model, into a parallel Handel-C description that utilizes the plurality of memory resources available on a realistic reconfigurable computing platform. the experimental results show that the latest generation of FPGAs, programmed using Handel-C, can achieve a sustained floating point performance up to 6 times greater than the microprocessor while operating at a clock frequency that is 60 times lower. the transformations are applied in a way that could be generalized, allowing efficient compilation approaches for the mapping of high level descriptions onto FPGAs.

关键词： field programmable gate arrays (FPGA)

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RAID 6 hardware acceleration

RAID 6 hardware acceleration

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16th international conference on field programmable logic and applications

作者： Gilroy, Michael Irvine, James Inst Syst Level Integrat Alba Campus Livingston EH54 Scotland Univ Strathclyde Mobile Commun Grp Glasgow G1 1XW Lanark Scotland

ISBN: (纸本)9781424403127

Hard disk storage capacity has continued to rise whilst at the same time the cost per megabyte continues to fall. this, combined with increased usage of digital storage for documents, photography and video for both home and business use has led to increased need for reliable data storage system. Redundant arrays of inexpensive disks (RAID) have proven to offer the best characteristics for reliable storage. However, to date RAID based systems have been limited, due to cost and circuit complexity, by their support for only single disk erasure tolerance. FPGAs allow us to overcome these difficulties and allow support for more complex storage algorithms. this paper introduces an efficient FPGA based hardware RAID 6 accelerator providing uninterrupted access during all single and double disk erasures and recovery.

关键词： field programmable gate arrays (FPGA)

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An FPGA implementation of high throughput stochastic simulator for large-scale biochemical systems

An FPGA implementation of high throughput stochastic simulat...

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16th international conference on field programmable logic and applications

作者： Yoshimi, Masato Osana, Yasunori Iwaoka, Yow Nishikawa, Yuri Kojima, Toshinori Funahashi, Akira Hiroi, Noriko Shibata, Yuichiro Iwanaga, Naoki Kitano, Hiroaki Amano, Hideharu Keio Univ Yokohama Kanagawa 223 Japan ERATO-SORST JST Kitano Symbiotic Syst Project Tokyo Japan Nagasaki Univ Nagasaki Japan

ISBN: (纸本)9781424403127

Stochastic simulation of biochemical systems has become one of major approaches to study life processes as system, yet is a computational challenge to run the simulation due to its vast calculation cost. this paper shows the implementation and evaluation of a stochastic simulation algorithm (SSA) called "First Reaction Method" on an FPGA-based biochemical simulator. It achieves high throughput by (1) consecutively throwing data into deeply-pipelined floating point arithmetic units, and (2) by distruibuting multiple simulators for parallel execution. As the result of evaluation on an FPGA-based simulation platform called ReCSiP2, the simulator outperforms execution on Xeon 2.80 GHz by approximately 80 times, even with large-scale biochemical systems.

关键词： field programmable gate arrays (FPGA)

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Reliable GALS implementation of MPEG-4 encoder with mixed clock FIFO on standard FPGA

Reliable GALS implementation of MPEG-4 encoder with mixed cl...

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16th international conference on field programmable logic and applications

作者： Kulmala, Ari Hamalainen, Timo D. Hannikainen, Marko Tampere Univ Technol Inst Digital & Comp Syst POB 553Korkeakoulunkatu 1 FI-33101 Tampere Finland

ISBN: (纸本)9781424403127

Globally Asynchronous Locally Synchronous (GALS) is a paradigm for complexity management and re-use of large System-on-Chip (SoC) architectures. GALS is most often based on specific ASIC design components or special FPGA platforms with custom development tools. In this paper we present a multiprocessor GALS implementation on a standard commercial FPGA with standard development tools. the key building block is a novel, reliable RTL mixed clock FIFO. A complete MPEG-4 video encoder with four processors is implemented for proofing the concept. the area overhead compared to a fully synchronous design is shown to be only 2% and the performance overhead is 3%. this is negligible compared to the benefits that are much better flexibility, ASIC or FPGA vendor independency, and reduced design time. Furthermore, the mixed-clock interfaces allow easy re-usability, since the RTL-level blocks do not need to be re-verfied in design iterations.

关键词： field programmable gate arrays (FPGA)

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An FPGA solver-for large SAT problems

An FPGA solver-for large SAT problems

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16th international conference on field programmable logic and applications

作者： Kanazawa, Kenji Maruyama, Tsutomu Univ Tsukuba Syst & Informat Engn 1-1-1 Ten Ou Dai Tsukuba Ibaraki 3058573 Japan

ISBN: (纸本)9781424403127

WSAT and its variants are one of the best performing stochastic local search algorithms for the satisfiability (SAT) problem. In this paper, we propose an FPGA solver for large SAT problems based on a WSAT algorithm. In hardware solvers, it is very important to solve large problems efficiently. In previous hardware solvers, all clauses are evaluated in parallel using the evaluators of the same number as the clauses to achieve high performance. In our solver, (1) only the clauses whose values will be changed are evaluated in parallel to minimize the circuit size, and (2) four independent tries are executed at the same time on the pipelined circuit to achieve high performance. Our FPGA solver can solve much larger problems than previous works with less hardware resources, and shows higher performance. the solver on XC2V6000 can solve problems up to 2000 variables and 8500 clauses.

关键词： field programmable gate arrays (FPGA)

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FPGA implementation and power modelling of the Fast Walsh Transform

FPGA implementation and power modelling of the Fast Walsh Tr...

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16th international conference on field programmable logic and applications

作者： Chandrasekaran, S. Amira, A. Brunel Univ Sch Engn & Design Elect & Comp Engn London UB8 3PH England

ISBN: (纸本)9781424403127

In this paper we present a novel design for an efficient FPGA architecture of Fast Walsh Transform (FWT) for hardware implementation of pattern analysis techniques such as projection kernel calculation and feature extraction. the proposed architecture is based on Distributed Arithmetic (DA) principles using ROM ACcumulate (RAC) technique and sparse matrix factorisation. the implementation has been carried out using a hybrid design approach based on Celoxica Handel-C which is used as a wrapper for highly optimised VHDL cores. the algorithm has been implemented and verified on the Xilinx Virtex-2000E FPGA. An evaluation has also been reported based on maximum system frequency and chip area for different system parameters, and have been shown to outperform existing work in all key performance measures. Additionally, a novel Functional Level Power Analysis and Modelling (FLPAM) methodology has been proposed to enable a high level estimation of power consumption.

关键词： field programmable gate arrays (FPGA)

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A codesign tool for high level systhesis of vision models on FPL

A codesign tool for high level systhesis of vision models on...

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16th international conference on field programmable logic and applications

作者： Martinez, Antonio Reynery, Leonardo Pelayo, Francisco Morillas, Christian Romero, Samuel Univ Alicante Dept Comp Technol Alicante Spain Polytecn Torino Dept Elect Turin Italy Univ Granada Dept Comp Engn E-18071 Granada Spain Univ Jaen Dept Comp Sci Jaen Spain

ISBN: (纸本)9781424403127

this paper presents a synthesis tool for the automatic translation and optimization of bioinspired vision models into a FPL implementation. the software allows functional simulation and high level specification of the model, and produces a data-flow model using VHDL, which is synthesizable with different lower-level synthesis tools and for various FPGA technologies. the proposed design platform extends the features of the codesign environment CodeSimulink for implementing visual processing systems, starting from purely functional specifications. An optimization strategy based on the calculation of the Pareto front is also introduced to perform a multi-objective minimization of both, the circuit area and the root mean square of the computation error. Performance measure-ments for the FPL implementation of an example retina-like vision model on a FPGA-based PCI board are provided.

关键词： field programmable gate arrays (FPGA)

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ON-FPGA COMMUNICATION ARCHITECTURES AND DESIGN FACTORS

<bold>ON-FPGA COMMUNICATION ARCHITECTURES AND DESIGN FACTORS...

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16th international conference on field programmable logic and applications

作者： Mak, Terrence S. T. Sedcole, Pete Cheung, Peter Y. K. Luk, Wayne Imperial Coll London Dept Elect & Elect Engn London SW7 2AZ England Imperial Coll London Dept Comp London England

ISBN: (纸本)9781424403127

the recent development of Platform-FPGA or field-programmable System-on-Chip architectures, with immersed coarse-grain processors, embedded memories and IP cores, offers the potential for immense computing power as well as opportunities for rapid system prototyping. these platforms require high-performance on-chip communication architectures for efficient and reliable inter-processor communication. However, as the number of embedded processors increases, communication bandwidth between embedded components becomes a limiting factor to overall system performance. In this paper, we survey the state-of-the-art on-FPGA communication architectures and methodologies. Salient factors, which include quantitative performance metrics and qualitative factors, relevant to design are identified and used to analyze and classify the on-FPGA communication architectures. this survey aims to facilitate innovation in and development of future on-FPGA communication architectures.

关键词： field programmable gate arrays (FPGA)

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Secure content distribution system based on run-time partial hardware reconfiguration

Secure content distribution system based on run-time partial...

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16th international conference on field programmable logic and applications

作者： Hori, Yohei Yokoyama, Hiroyuki Toda, Kenji AIST 1-1-1 Umezono Tsukuba Ibaraki Japan KDDI R&D Lab Inc Saitama 3568502 Japan

ISBN: (纸本)9781424403127

A secure content distribution system is prototyped based on run time partial reconfigurability of an FPGA. the system provides a robust content protection scheme for online con tent download services. the key idea is to divide the security module in a user terminal into ontent Specific ircuit (S) and Terminal uild in ircuit (T) and to dynamically reconfigure S. S is customi ed for each content and transferred from a server in the form of encrypted con figuration data. T is a uniquely identifiable processing unit that is combined with particular S to decrypt and de code contents. A content is properly decrypted and played by the security module only if its S is interlocked with the authori ed T To reali e this S T interlock authen tication mechanism, partial reconfigurability of the FPGA is essential. this paper discusses the robustness and feasibility of the content distribution system through a proof of concept demonstration.

关键词： field programmable gate arrays (FPGA)

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