检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,876 篇 会议
30 篇 期刊文献
7 册 图书

馆藏范围

1,913 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,244 篇 工学
- 1,042 篇 计算机科学与技术...
- 729 篇 软件工程
- 407 篇 电气工程
- 183 篇 电子科学与技术（可...
- 74 篇 信息与通信工程
- 63 篇 控制科学与工程
- 33 篇 仪器科学与技术
- 30 篇 机械工程
- 26 篇 动力工程及工程热...
- 23 篇 建筑学
- 17 篇 土木工程
- 15 篇 核科学与技术
- 13 篇 光学工程
- 13 篇 生物工程
- 10 篇 材料科学与工程（可...
- 10 篇 生物医学工程（可授...
- 8 篇 安全科学与工程
171 篇 理学
- 101 篇 数学
- 45 篇 物理学
- 18 篇 生物学
- 17 篇 系统科学
- 9 篇 统计学（可授理学、...
- 6 篇 化学
49 篇 管理学
- 38 篇 管理科学与工程(可...
- 19 篇 工商管理
- 14 篇 图书情报与档案管...
16 篇 医学
- 14 篇 临床医学
- 12 篇 特种医学
14 篇 法学
- 12 篇 社会学
9 篇 经济学
- 9 篇 应用经济学
5 篇 农学
5 篇 军事学
2 篇 教育学

主题

834 篇 field programmab...
688 篇 field programmab...
276 篇 hardware
157 篇 computer archite...
126 篇 logic gates
112 篇 table lookup
87 篇 throughput
87 篇 clocks
83 篇 random access me...
79 篇 routing
74 篇 software
72 篇 acceleration
66 篇 delays
65 篇 optimization
62 篇 kernel
54 篇 registers
54 篇 logic
50 篇 switches
49 篇 algorithm design...
47 篇 system-on-chip

机构

14 篇 univ toronto dep...
9 篇 imperial coll lo...
8 篇 school of comput...
8 篇 department of co...
8 篇 ecole polytech f...
7 篇 univ british col...
7 篇 brigham young un...
7 篇 imperial coll lo...
7 篇 tokyo inst techn...
6 篇 univ tsukuba tsu...
6 篇 university of ch...
6 篇 department of el...
6 篇 univ warwick sch...
6 篇 xilinx inc san j...
5 篇 univ manchester ...
5 篇 department of el...
5 篇 univ toronto dep...
5 篇 inesc-id univers...
5 篇 swiss fed inst t...
5 篇 department of el...

作者

31 篇 luk wayne
21 篇 maruyama tsutomu
16 篇 koch dirk
14 篇 wayne luk
12 篇 wilton steven j....
12 篇 ienne paolo
11 篇 betz vaughn
10 篇 fahmy suhaib a.
10 篇 cheung peter y. ...
9 篇 vaughn betz
9 篇 constantinides g...
9 篇 prasanna viktor ...
9 篇 amano hideharu
8 篇 paolo ienne
8 篇 chow paul
8 篇 akash kumar
7 篇 kapre nachiket
7 篇 teich juergen
7 篇 suhaib a. fahmy
7 篇 alonso gustavo

语言

1,885 篇 英文
24 篇 其他
4 篇 中文

检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

共 1913 条记录，以下是1581-1590 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Real-time K-Means Clustering for Color Images on Reconfigurable Hardware

Real-time K-Means Clustering for Color Images on Reconfigura...

引用

international conference on Pattern Recognition

作者： T. Maruyama Systems and Information Engineering University of Tsukuba Tsukuba Ibaraki Japan

K-means clustering is a very popular clustering technique, which is used in numerous applications. However, clustering is a time consuming task, particularly for large dataset, and large number of clusters. In this paper, we show that real-time k-means clustering can be realized for large size color images (24-bit full color RGB) and large number of clusters (up to 256) using an off-the-shelf FPGA (field programmable gate arrays) board. In our current implementation with one FPGA, the performance for 512 times 512 and 640 times 480 pixel images is more than 30fps, and 20-30 fps for 756 times 512 pixel images in average when dividing to 256 clusters

关键词： Color Hardware field programmable gate arrays Clustering algorithms Circuits Software algorithms Pixel Filtering algorithms Software performance Systems engineering and theory

来源：评论

学校读者我要写书评

暂无评论

Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures

Wire Segment Length and Switch Box Co-Optimization for FPGA ...

引用

international conference on field programmable logic and applications

作者： Kostas Siozios Dimitrios Soudris VLSI Design and Testing Center Department of Electrical and Computer Engineering Democritus University of Thrace Xanthi Greece

the novel methodology for designing a high-performance and low-energy FPGA interconnection architecture consisting of appropriate wire segments and multiple switch boxes is introduced. Depending on the localized performance and energy consumption requirements of each specific region of FPGA architecture, we derive a set of corresponding spatial routing information of the applications mapped onto reconfigurable device. In this paper, an interconnection network with segments L1&L2 and 3 different switch box regions is used. the selection criterion for our approach is the minimal energytimesdelay product (EDP). the proposed methodology is fully-supported by the software tool called EX-VPR. With this interconnection architecture we achieved EDP reduction by 56%, performance increase by 47%, reduction in leakage power by 18%, reduction in total energy consumption by 9%, at the expense of increase of channel width by 15% compared to conventional FPGA architectures

关键词： Switches Wire field programmable gate arrays Energy consumption Computer architecture Design methodology Routing Application software Multiprocessor interconnection networks Software tools

来源：评论

学校读者我要写书评

暂无评论

Reconfigurable System with Virtuoso Real-Time Kernel and TEV Environment

Reconfigurable System with Virtuoso Real-Time Kernel and TEV...

引用

international Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

作者： M. C. Andrade C. E. Moron J. H Saito UFSCar – Universidade Federal de São Carlos

this paper presents an easy procedure to develop a reconfigurable application in a Virtuoso real-time operating system using the visual environment TEV developed at DC/UFSCar. In TEV, applications are built using graphs, where nodes are data structures that compose a parallel program (tasks, signals, resources, mailboxes, etc.), and arrows denote the communication and synchronization operations between the data structures. the information in the graphical model can be complemented with code written by the user. Based on this construction, the source code of the application is automatically generated. this paper describes a proposal of the TEV extension with reconfigurable applications, denoting R-TEV, using a reconfigurable functions library. A case study is presented, using three reconfigurable functions, and the results show that the proposal is feasible

关键词： Real time systems Kernel Hardware Computer architecture Proposals Programming profession Data structures Application software field programmable gate arrays Reconfigurable logic

来源：评论

学校读者我要写书评

暂无评论

Future FPGA technologies, in partnership with universities

Future FPGA technologies, in partnership with universities

引用

international conference on VLSI Design

作者： R. Sevcik Programmable Logic Systems Group Software Solutions Group

Summary form only given. Over the last few years, significant technical advances have increasingly made field programmable gate arrays (FPGAs) the mainstream solution of choice for many digital system designers. this presentation talks about current and future design technologies that enable FPGAs to be used in an ever-increasing range of applications like embedded systems, digital signal processing, and high-speed serial communication, in addition to traditional logic design. It covers the aggressive adoption of process technology in FPGAs, with products in 65 nm technology scheduled for 2006. this talk also presents some of the work done with universities across the globe (and in India) to help further education and research in the area of programmable technologies.

关键词：

来源：评论

学校读者我要写书评

暂无评论

the Reconfigurable Computing Applied to the Learning in the Computer Engineering Program

The Reconfigurable Computing Applied to the Learning in the ...

引用

international conference on Information Technology Based Higher Education and Training, IthET

作者： Valfredo Pilla Edson P. Ferlin Computer Engineering Department UnicenP-Centro Universitário Positivo Rua Prof Pedro Viriato Parigot de Souza 5300-Campo Comprido-Curitiba-PR Brazil E. P. Ferlin Chair Computer Engineering Department Centro Universitário Positivo - UnicenP Brazil

the reconfigurable computing has an increasing importance in the computational solutions because of its two mains characteristics: performance and flexibility. this became possible with the technological advance of the programmable logic devices (PLDs) and the field programmable gate array (FPGAs), which makes possible an increasing level of system integration (hardware and software). this integration can allow the construction of a complex system in a single device, the system on chip (SoC) technology. this is a multidisciplinary area, because it involves digital systems projects (some time analog systems also), firmware and operational systems development, beyond the specific knowledge of the areas of the systems applications. For this reasons the reconfigurable computation became part of the computer engineer formation. It is imperative that the new professionals have complete domain of this technology to be able to integrate it in the new computational systems. these computational systems reach a wide range of applications, from high performance computing to embedded systems, personal and mobile computation, to entertainment and mobile communication. In this direction, we present the evolution that happened in the Computer Engineering Program at UnicenP from the adoption of the technology of PLDs and FPGAs in several courses, and the inclusion of a specific course of reconfigurable computing.

关键词： field programmable gate arrays High performance computing programmable logic arrays Application software Embedded computing programmable logic devices field programmable analog arrays Hardware System-on-a-chip Digital systems

来源：评论

学校读者我要写书评

暂无评论

Construction of FPGA Based Hardware Controller for Autonomous Decentralized Control for UPS Application

Construction of FPGA Based Hardware Controller for Autonomou...

引用

international (EPE-PEMC) Power Electronics and Motion Control conference

作者： Wataru Fujii Tomoki Yokoyama Tokyo Denki University Hiki Saitama Japan

Design concept of FPGA based hardware controller is proposed with basic modules for the development of power electronics applications. Also an autonomous decentralized control system for single phase UPS inverter with FPGA based hardware controller using software CPU core is described. Progress of FPGA technology makes it possible to include the software macro CPU core into the FPGA chip, a high flexibility can be realized for the construction of the control processor in power electronics application. But the basic modules for power electronics application are not enough in the environment of FPGA development platform. In this paper, several modules are presented for power electronics applications, and also proposed an autonomous distributed control system for single phase UPS inverter with FPGA based hardware controller using CPU core. the advantages of FPGA based hardware control system are discussed.

关键词： field programmable gate arrays Hardware Distributed control Uninterruptible power systems Control systems Power electronics Application software Circuits Read-write memory logic

来源：评论

学校读者我要写书评

暂无评论

the Case Study of Block Turbo Decoders on a Framework for Portable Synthesis on FPGA

The Case Study of Block Turbo Decoders on a Framework for Po...

引用

Annual Hawaii international conference on System Sciences (HICSS)

作者： C. Dezan C. Jego B. Pottier C. Gouyen L. Lagadec LESTER/AS (CNRS) Université de Bretagne Occidentale France GET/ENST Bretagne TAMCIC (CNRS) France

On the case study of block turbo decoders for error correction, the paper shows that the use of unconventional framework like Madeo can produce interesting FPGA implementations. Error correction algorithms are known to be very important for communication data rate and reliability. As reconfigurable architectures are attractive for fast prototyping and flexibility, they are often considered as support for implementation of communication, including mobile communication. Madeo is an open framework for designing physical FPGA architectures and their applications. On the basis of an abstract model for reconfigurable circuits, Madeo provides the necessary tools (logic synthesis and physical tool) to program them. the paper describes the block turbo decoder principle, discusses existing solutions and presents characteristics of a partial implementation on the open framework Madeo. three elements of a block turbo decoder have been designed using Madeo and the physical solutions compete very well with existing solutions for such problems.

关键词： Computer aided software engineering Decoding field programmable gate arrays Error correction Mobile communication Circuit synthesis Arithmetic Error correction codes Channel coding Turbo codes

来源：评论

学校读者我要写书评

暂无评论

Combined Integer and Floating Point Multiplication Architecture(CIFM) for FPGAs and Its Reversible logic Implementation

Combined Integer and Floating Point Multiplication Architect...

引用

Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Himanshu thapliyal Hamid R. Arabnia A.P Vinod Centre for VLSI Design Indian Institute of Technology Hyderabad India Department of Computer Science University of Georgia USA School of Computer Engineering Nanyang Technological University Singapore

In this paper, the authors propose the idea of a combined integer and floating point multiplier (CIFM) for FPGAs. the authors propose the replacement of existing 18times18 dedicated multipliers in FPGAs with dedicated 24times24 multipliers designed with small 4times4 bit multipliers. It is also proposed that for every dedicated 24times24 bit multiplier block designed with 4times4 bit multipliers, four redundant 4times4 multiplier should be provided to enforce the feature of self repairability (to recover from the faults). In the proposed CIFM reconfigurability at run time is also provided resulting in low power. the major source of motivation for providing the dedicated 24times24 bit multiplier stems from the fact that single precision floating point multiplier requires 24times24 bit integer multiplier for mantissa multiplication. A reconfigurable, self-repairable 24times24 bit multiplier (implemented with 4times4 bit multiply modules) will ideally suit this purpose, making FPGAs more suitable for integer as well floating point operations. A dedicated 4times4 bit multiplier is also proposed in this paper. Moreover, in the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. It is not possible to realize quantum computing without reversible logic. thus, this paper also paper provides the reversible logic implementation of the proposed CIFM. the reversible CIFM designed and proposed here will form the basis of the completely reversible FPGAs.

关键词： field programmable gate arrays Quantum computing Digital signal processing CMOS logic circuits Optical computing Signal processing algorithms logic design Very large scale integration Computer science Design engineering

来源：评论

学校读者我要写书评

暂无评论

An Efficient H.264 VLSI Advanced Video Encoder

An Efficient H.264 VLSI Advanced Video Encoder

引用

13th IEEE international conference on Electronics, Circuits and Systems (ICECS'2006), vol.2

作者： K. Babionitakis G. Lentaris K. Nakos D. Reisis N. Vlassopoulos G. Doumenis G. Georgakarakos J. Sifnaios Electronics Laboratory Department of Physics National and Kapodistrian University of Athens Athens Greece Global Digital Technologies Athens Greece

Video technology evolution has boosted the need for the H.264/AVC encoder with real-time performance. In order to meet such need the present paper presents a VLSI H.264/AVC encoder architecture and the relevant details on design and implementation of the specific modules. the encoder design complies with the reference software encoder of the standard and follows the baseline profile level 3.0. the encoder constitutes an IP-core and/or stand-alone solution targeting to low area applications. the architecture achieves maximum throughput of 30 frames/sec with frame size 1024×768. Results and performance measurements of the entire encoder have been validated on FPGA and VLSI .18μm.

关键词： Very large scale integration Encoding Automatic voltage control throughput Computer architecture Software standards field programmable gate arrays Pipeline processing Clocks Quantization

来源：评论

学校读者我要写书评

暂无评论

Multiple fault testing of logic resources of SRAM-based FPGAs

Multiple fault testing of logic resources of SRAM-based FPGA...

引用

18th international conference on VLSI Design/4th international conference on Embedded Systems Design

作者： Goyal, S Choudhury, M Rao, SSSP Kumar, K Indian Inst Technol Bombay 400076 Maharashtra India

ISBN: (纸本)0769522645

We shall present a simple but useful method which detects all multiple stuck-at faults in the application and configuration inputs of LUTs. A novel method for testing of stuck-at faults at control bits of flip flops has also been proposed. the aim is to integrate testing of LUTs, flip flops and multiplexers which will reduce the number of configurations and hence minimize the testing time.

关键词： field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共192页 << < 155 156 157 158 159 160 161 162 163 164 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：