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检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

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FELIX: using rewriting-logic for generating functionally equivalent implementations

FELIX: using rewriting-logic for generating functionally equ...

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international conference on field programmable logic and applications

作者： C. Morra J. Becker M. Ayala-Rincon R. Hartenstein ITIV Universität Karlsruhe (TH) Karlsruhe Germany Departamento de Matemática Universidade de Brasília Brasília Brazil Fachbereich Informatik TU Kaiserslautern Kaiserslautern Germany

FELIX is a new design space exploration tool and graphical integrated development environment (IDE) for the programming of coarse-grained reconfigurable architectures. Its main and novel advantage is the use of rewriting rules and logical strategies for the automated generation of alternative functionally equivalent implementations from a single mathematical specification. the user selection of the rewriting logic strategies to be applied determines the resulting implementations, making it possible to quickly generate, simulate and evaluate alternative implementations that are logically equivalent. the FELIX system includes an interface to the KressArray Xplorer for hardware design-space exploration. the current version of the tool is targeted for the pact extreme processing platform (XPP), with support for additional architectures planned in future versions.

关键词： Hardware Reconfigurable logic logic programming Computer architecture Reconfigurable architectures Systolic arrays Prototypes Application software Mathematics Space exploration

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Measuring and utilizing the correlation between signal connectivity and signal positioning for FPGAs containing multi-bit building blocks

Measuring and utilizing the correlation between signal conne...

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international conference on field programmable logic and applications

作者： A. Ye J. Rose Department of Electrical and Computer Engineering University of Toronto Toronto ONT Canada

As the logic capacity of FPGA increases, there has been a corresponding increase in the variety of FPGA building blocks. From a mere collection of the conventional logic blocks, FPGAs now can include digital signal processors, multipliers, multi-bit addressable memory cells, and even processor cores; and one of the common characteristics of these new building blocks is their multi-bit design, where each block is designed specifically to process several bits of data at a time. this multi-bit processing paradigm is significantly different from the single-bit processing design of the conventional FPGA logic blocks; and it creates differentiation in signals through its bussed structures. Consequently, this paper examines the correlation between the positions of the signals in buses and the connectivity of these signals. Based on the correlation measurements, a multi-bit routing architecture is then proposed along with its routing tool. It is experimentally shown that, comparing to the conventional routing architectures, the multi-bit architecture requires 12% less area to implement; and in particular, it needs 27% less routing switches to connect its multi-bit blocks to their routing tracks, and 18% less configuration memory to store the configuration information.

关键词： Position measurement field programmable gate arrays Routing Signal processing logic circuits Statistics Clustering algorithms Strontium Educational institutions Switching circuits

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Two-stage reconfigurable computing system architecture

Two-stage reconfigurable computing system architecture

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IEEE international conference on Systems Engineering

作者： Yan-Xiang Deng Chao-Jang Hwang Der-Chyuan Lou Department of Computer Science and Engineering Yuan-Ze University Taoyuan Taiwan Department of Electrical Engineering Chung ChEngineering Institute of Technology National Defense University Taoyuan Taiwan

there are many successful applications of reconfigurable computing architecture. they can be implemented into reconfigurable computing system according to their function algorithms usually. But, due to the influence of Gordon Moore's Law on FPGA (field programmable gate arrays) structure, the gate array sizes have been expanded widely under the technology of VLSI (ultra large scale integration). So, Using FPGAs to implement the design of function level is waste of reconfigurable units. therefore, how to build a powerful reconfigurable computing architecture is an important research topic. In this article, a new reconfigurable computing architecture named TSRCS (two-stage reconfigurable computing system) is proposed. the concept of TSRCS is to split the reconfiguration into two stages, one is SSR (system-stage reconfiguration) and another is FSR (function-stage reconfiguration). the SSR dynamically rebuilds routing networks that connect between RFBs (reconfigurable function blocks) but the FSR busily reconfigures RFBs following some computing algorithm that we want to do. the TSRCS can dynamic change not only the system architecture but also any function. the advantages of using TSRCS to implement a system are flexible architecture, varied functions, open system, and changeable performance but the disadvantage is longer construction. In this paper, a new design method is proposed which can combine the forte of software and hardware to build a new system architecture and the research results have important contribution to computer science.

关键词： Computer architecture field programmable gate arrays Computer applications Moore's Law Very large scale integration Ultra large scale integration Routing Computer networks Open systems Design methodology

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14th international conference on field programmable logic and applications, FPL, 2004

14th International Conference on Field Programmable Logic an...

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14th international conference on field programmable logic and applications, FPL 2004

ISBN: (纸本)3540229892

the proceedings contain 177 papers. the special focus in this conference is on Plenary Keynotes;Organic and Biology Computing;Security and Cryptography;Platform Based Design. the topics include: FPGAs and the Era of field Programmability;Reconfigurable Systems Emerge;System-Level Design Tools Can Provide Low Cost Solutions in FPGAs;Hardware Accelerated Novel Protein Identification;Large Scale Protein Sequence Alignment Using FPGA Reprogrammable logic Devices;A Key Management Architecture for Securing Off-Chip Data Transfers;FPGA Implementation of Biometric Authentication System Based on Hand Geometry;A Customisable Modular Platform for Video applications;Deploying Hardware Platforms for SoC Validation;Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes;Power Analysis Attacks Against FPGA Implementations of the DES;Monte Carlo Radiative Heat Transfer Simulation on a Reconfigurable Computer;Stochastic Simulation for Biochemical Reactions on FPGA;Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures;Interconnecting Heterogeneous Nodes in an Adaptive Computing Machine;Improving FPGA Performance and Area Using an Adaptive logic Module;A Dual-VDD Low Power FPGA Architecture;Simultaneous Timing Driven Clustering and Placement for FPGAs;Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis;Compact Buffered Routing Architecture;On Optimal Irregular Switch Box Designs;An Efficient Alternative to Floating-Point Computation;Comparative Study of SRT-Dividers in FPGA;Second Order Function Approximation Using a Single Multiplication on FPGAs;Efficient Modular Division Implementation and A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management.

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FPGA implementation of the ridge line following fingerprint algorithm 14th

FPGA implementation of the ridge line following fingerprint ...

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14th international conference on field-programmable logic and applications

作者： Cantó, E Canyellas, N Fons, M Fons, F López, M URV ETSE Tarragona Spain

Most biometrics systems are implemented on high performance microprocessors executing complex algorithms on software. In order to develop a low-cost and high-speed coprocessor, floating-point computations have been su... 详细信息

ISBN: (纸本)3540229892

关键词： field programmable gate arrays (FPGA)

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A low power FPAA for wide band applications 14th

A low power FPAA for wide band applications

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14th international conference on field-programmable logic and applications

作者： Schüler, E Carro, L Univ Fed Rio Grande Sul Dept Engn Elet Porto Alegre RS Brazil

ISBN: (纸本)3540229892

the necessity for programmable analog devices appears when it is necessary to ease the design process in small time and with minimum costs, making the research in FPAAs (field programmable Analog Array) more intense. In this work we proposed a new FPAA topology aiming at wide frequency range, while keeping a high degree of reconfigurability. the impact in frequency, programmability and resolution are evaluated, showing that the proposed technique gives a good performance in these aspects.

关键词： Computers

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Multithreading in a hyper-programmable platform for networked systems 14th

Multithreading in a hyper-programmable platform for networke...

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14th international conference on field-programmable logic and applications

作者： James-Roxby, P Brebner, G Xilinx Research Labs Xilinx Inc United States

ISBN: (纸本)3540229892

Modem programmable logic devices have capabilities that are well suited for them to assume a central role in the implementation of networked systems. We have devised a highly flexible soft platform architecture abstracted from such physical devices, which may be viewed as a particularly configurable, and programmable type of network processor. In this paper, we discuss multithreading in the context of this logic-centric soft platform, and describe the programmable mechanisms to support multithreading that we have implemented. through a design example, we evaluate these mechanisms, and report that the solution obtained had comparable performance to a custom solution written from scratch without the intermediate soft platform.

关键词： logic devices

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FPGA-efficient hybrid LUT/CORDIC architecture 14th

FPGA-efficient hybrid LUT/CORDIC architecture

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14th international conference on field-programmable logic and applications

作者： Janiszewski, I Meuth, H Hoppe, B Univ Appl Sci Darmstadt Fachhsch D-64295 Darmstadt Germany

ISBN: (纸本)3540229892

the paper presents a hybrid architecture for digital polar-to-Cartesian (i.e. phase-to-I/Q) designs. the hybrid LUT/CORDIC architecture allows design partitioning between logic and storage based FPGA resources. FPGA resource utilization, timing and power consumption as well as accuracy of calculated results may be optimised consistently in comparison to conventional pure CORDIC algorithm implementations.

关键词： field programmable gate arrays (FPGA)

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SystemC for the design and modeling of programmable systems 14th

SystemC for the design and modeling of programmable systems

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14th international conference on field-programmable logic and applications

作者： Donlin, A Braun, A Rose, A Xilinx Res Labs San Jose CA 95124 USA Univ Tubingen Dept Commun Engn D-72076 Tubingen Germany Cadence Design Syst Manchester Lancs England

ISBN: (纸本)3540229892

the field programmable logic (FPL) community is set to assume an important role within the electronic system level (ESL) community. programmable technologies are proving to be the correct implementation substrate for the growing majority of system architects who can no longer afford the cost or shoulder the risks associated with submicron ASIC design. In this tutorial we present an overview of SystemC, the dominant and open environment for ESL design and modeling. We focus on presenting the fundamentals of the language and describing an important extension to the language that enables rapid modeling of systems at the transaction level.

关键词： System theory

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Implementation of the extended Euclidean algorithm for the tate pairing on FPGA 14th

Implementation of the extended Euclidean algorithm for the t...

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14th international conference on field-programmable logic and applications

作者： Ito, T Shibata, Y Oguri, K Nagasaki Univ Dept Comp & Informat Sci Nagasaki Japan

ISBN: (纸本)3540229892

the Tate pairing is a mapping which has good functionality for constructing elliptic cryptosystems, while its computation is a hard task. Especially, calculation of an inverse element using the extended Euclidean algorithm over a finite field F-p tends to be a bottleneck. In this paper, several kinds of implementation of the extended Euclidean algorithm on an FPGA are shown and compared. Effects of introducing Montgomery multiplication methods are also analyzed.

关键词： field programmable gate arrays (FPGA)

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