this paper describes the synthesis of dynamic differential logic to increase the resistance of FPGAs against Differential Power Analysis. Compared with an existing technique, it saves more than a factor 2 in slice uti...
详细信息
ISBN:
(纸本)3540229892
this paper describes the synthesis of dynamic differential logic to increase the resistance of FPGAs against Differential Power Analysis. Compared with an existing technique, it saves more than a factor 2 in slice utilization. Experimental results indicate that a secure version of the AES algorithm can now be implemented with a mere doubling of the slice utilization when compared with a normal non-secure single ended implementation.
A novel configuration bitstream generation tool for a custom FPGA platform is presented. It can support a variety of devices of similar architecture. the tool exhibits technology independence and is easily modifiable....
详细信息
ISBN:
(纸本)3540229892
A novel configuration bitstream generation tool for a custom FPGA platform is presented. It can support a variety of devices of similar architecture. the tool exhibits technology independence and is easily modifiable. the tool also allows partial reconfiguration as long as the target platform also does.
Speculation and parallel processing can provide performance gains in many diverse applications. Compilers, grid computing, DSP, and bio-informatics are a representation of such areas where these concepts are utilized....
ISBN:
(纸本)3540229892
Speculation and parallel processing can provide performance gains in many diverse applications. Compilers, grid computing, DSP, and bio-informatics are a representation of such areas where these concepts are utilized. In the field of network routers, packet processing can also use such speedups. As the line rate of packets increases with every new standard (Infiniband, 10-gigabit Ethernet), these speedups will become paramount for routers asked to do complicated tasks while still maintaining line speeds.
In this paper, we present a technique and a tool to debug microprocessor systems implemented in FPGAs. We propose a method based on debug logic insertion and a set of debug modules to provide soft core microprocessors...
详细信息
ISBN:
(纸本)3540229892
In this paper, we present a technique and a tool to debug microprocessor systems implemented in FPGAs. We propose a method based on debug logic insertion and a set of debug modules to provide soft core microprocessors with In-Circuit Emulation capabilities.
Real-time performance of adaptive digital signal processing algorithms is required in many applications but it often means a high computational load for many conventional processors. In this paper, we present a config...
详细信息
ISBN:
(纸本)3540229892
Real-time performance of adaptive digital signal processing algorithms is required in many applications but it often means a high computational load for many conventional processors. In this paper, we present a configurable hardware architecture for adaptive processing of noisy signals for target detection based on Constant False Alarm Rate (CFAR) algorithms. the architecture has been designed to deal with parallel/pipeline processing and to be configured for three versions of CFAR algorithms, the Cell-Average, the Max and the Min CFAR. the architecture has been implemented on a fieldprogrammable Gate Array (FPGA) with a good performance improvement over software implementations. Results are presented and discussed.
the paper describes two methods for the design of matrix-oriented SAT solvers based on data compression. the first one provides matrix compression in a host computer and decompression in an FPGA. It is shown that alth...
详细信息
ISBN:
(纸本)3540229892
the paper describes two methods for the design of matrix-oriented SAT solvers based on data compression. the first one provides matrix compression in a host computer and decompression in an FPGA. It is shown that although some improvements have been achieved in this case, there exists a better solution. the second method makes possible to execute operations required for solving the SAT problem over compressed matrices.
Overtaking is one of the most dangerous operations in driving. the rear-view mirror is sometimes not consulted by the driver or is momentarily useless because of the blind spot. this paper describes a simple FPGA syst...
详细信息
ISBN:
(纸本)3540229892
Overtaking is one of the most dangerous operations in driving. the rear-view mirror is sometimes not consulted by the driver or is momentarily useless because of the blind spot. this paper describes a simple FPGA system based on motion detectors of the fly and rigid-body detection that is able to efficiently segment overtaking cars using a sparse map of features from the visual field of the rear-view mirror. FPGA implementation allows real-time image processing on an embedded system.
this paper presents two novel architectures for efficient implementation of a Color Space Converter (CSC) suitable for fieldprogrammable Gate Array (FPGAs) and VLSI. the proposed architectures are based on Distribute...
详细信息
ISBN:
(纸本)3540229892
this paper presents two novel architectures for efficient implementation of a Color Space Converter (CSC) suitable for fieldprogrammable Gate Array (FPGAs) and VLSI. the proposed architectures are based on Distributed Arithmetic (DA) ROM accumulator principles. the architectures have been implemented and verified using the Celoxica RC1000-PP FPGA development board. In addition, they are platform independent and have a low latency (8 cycles). the first architecture has a throughput of height, while the second one is fully pipelined and has a throughput of one and capable of sustained data rate of over 234 mega-conversions/seconds.
A method for testability-oriented optimization of sequential circuits implemented using FPGAs with embedded memory is presented. It specifies the content of those memory words which are not defined by the conventional...
详细信息
ISBN:
(纸本)3540229892
A method for testability-oriented optimization of sequential circuits implemented using FPGAs with embedded memory is presented. It specifies the content of those memory words which are not defined by the conventional FSM synthesis. the experimental results confirm its effectiveness;for the largest examined circuit, the self-test session required to achieve an acceptable level of fault escapes for the optimized design, obtained using the proposed procedure, is almost 10(6) times shorter than for the non-optimized design. the proposed method does not involve any extra circuitry or speed degradation. Also, it does not require any extra reconfiguration during self-testing.
the length of the longest common subsequence (LCS) between two strings of M and N characters can be computed by O(M x N) dynamic programming algorithms that can execute in O(M + N) on a linear systolic array. If the s...
详细信息
ISBN:
(纸本)3540229892
the length of the longest common subsequence (LCS) between two strings of M and N characters can be computed by O(M x N) dynamic programming algorithms that can execute in O(M + N) on a linear systolic array. If the strings axe run-length encoded, LCS can be computed by an O(mN + Mn - mn) algorithm, called RLE-LCS, where m and n are the numbers of runs of the two strings. In this paper we propose a modified RLE-LCS algorithm mappable on a linear systolic array.
暂无评论