Increasing logic resources coupled with a proliferation of integrated performance enhancing primitives in high-end FPGAs results in an increased design complexity which requires new methodologies to overcome. this pap...
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ISBN:
(纸本)3540229892
Increasing logic resources coupled with a proliferation of integrated performance enhancing primitives in high-end FPGAs results in an increased design complexity which requires new methodologies to overcome. this paper presents a structured system based design methodology, centred around the concept of architecture reuse, which aims to increase productivity and exploit the reconfigurability of high-end FPGAs. the methodology is exemplified by the Sonic-on-a-Chip architecture. Preliminary experimental investigations reveal that while the proposed methodology is able to achieve the desired aims, its success would be enhanced if changes were made to existing FPGA fabrics in order to make them better suited to modular design.
In this paper, we propose a new area-efficient logic module architecture for SRAM-based FPGAs. this new architecture is motivated by the analysis results of some LUT-level benchmarks. the analysis results indicate tha...
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ISBN:
(纸本)3540229892
In this paper, we propose a new area-efficient logic module architecture for SRAM-based FPGAs. this new architecture is motivated by the analysis results of some LUT-level benchmarks. the analysis results indicate that a large percentage of the LUTs in a LUT-level circuit are permutation (P) equivalent (not even including input negations or output negations, called NPN equivalences in the literature, or constant assignments). the proposed logic module utilizes lookuptable sharing among two or more basic logic elements (BLEs) in a cluster, as opposed to one LUT per BLE. Preliminary results indicate that almost half of the LUTs are eliminated in all benchmarks. this great area reduction would reflect to the cost and prices of FPGAs and also would strengthen the FPGA usage in applicationsthat have rigid area constraints such as an FPGA within a hearing aid.
Microcontrollers and ASICs have become a dominant part during the last years in the development of embedded applications like automotive control units. As described in our previous contribution we presented an alterna...
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ISBN:
(纸本)3540229892
Microcontrollers and ASICs have become a dominant part during the last years in the development of embedded applications like automotive control units. As described in our previous contribution we presented an alternative approach exploiting the possibilities of partial run-time reconfiguration of state-of-the-art Xilinx Virtex FPGAs. Our approach used a run-time system software for controlling reconfiguration and message handling. this paper presents some new extensions introducing dynamic priority measures as a first approach for adaptive reconfiguration decisions.
the progress of the semiconductor industry over the last several decades has been described as a series of alternating cycles of standardization and customization. According to Makimoto’s wave, as the model is known,...
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Modeling of molecule interactions often uses rigid models and correlation techniques, either in early screening passes or as steps within more complex models. Even rigid models are time-consuming when applied to large...
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ISBN:
(纸本)3540229892
Modeling of molecule interactions often uses rigid models and correlation techniques, either in early screening passes or as steps within more complex models. Even rigid models are time-consuming when applied to large models at 10(3) - 10(5) different three-axis rotations. this paper presents an FPGA structure for performing the correlations efficiently using a systolic array for 3-D correlation and an addressing technique for low-overhead rotation of a 3-D voxel models around three axes. We find a 200x speedup in our FPGA implementation compared to the standard transform-based method.
As the logic capacity of field-programmable Gate Arrays (FPGAs) increases, they are being increasingly used to implement large arithmetic-intensive applications, which often contain a large proportion of datapath circ...
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Withthe help of the FPGA technology, the boarder between hard- and software has vanished. It is now possible to develop complex designs and fine grained parallel applications without the long-lasting chip design cycl...
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ISBN:
(纸本)3540229892
Withthe help of the FPGA technology, the boarder between hard- and software has vanished. It is now possible to develop complex designs and fine grained parallel applications without the long-lasting chip design cycles. Additionally, it has become easier to write coarse grained parallel applications withthe help of message passing libraries like MPI. the chess program Hydra is a high level hardware-software co-design application which profits from both worlds. We describe the design philosophy, general architecture and performance of Hydra. the time critical part of the search tree, near the leaves, is explored withthe help of fine grain parallelism of FPGA cards. For nodes near the root, the search algorithm runs distributed on a cluster of conventional processors. A nice detail is that the FPGA cards allow the implementation of sophisticated chess knowledge without decreasing the computational speed.
Dynamically reconfigurable devices allow run-time reconfiguration. to permit, execution of incoming tasks or task fragments. One of the important issues in run-time reconfiguration is the fragmentation of the device a...
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ISBN:
(纸本)3540229892
Dynamically reconfigurable devices allow run-time reconfiguration. to permit, execution of incoming tasks or task fragments. One of the important issues in run-time reconfiguration is the fragmentation of the device area as the reconfigurable blocks are allocated and released when tasks are placed;executed and deleted. Due to those scattered, unused resources, an incoming application may not be placeable or routable. A cluster-based reconfigurable FPGA architecture is proposed to alleviate this difficulty. We present an assessment of the proposed architecture. We develop a fast evaluation tool to simulate on-line placement and routing effects on a run-time reconfigurable platform. the simulation results show the efficiency,of the proposed architecture in relieving the fragmentation problem at the price of a modest increase in the number of switches.
Reconfigurable Computers are general-purpose high-end computers based on a hybrid architecture and close system-level integration of traditional microprocessors and fieldprogrammable Gate Arrays (FPGAs). In this pape...
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ISBN:
(纸本)3540229892
Reconfigurable Computers are general-purpose high-end computers based on a hybrid architecture and close system-level integration of traditional microprocessors and fieldprogrammable Gate Arrays (FPGAs). In this paper, we present an application of reconfigurable computers to developing a low-latency implementation of Elliptic Curve Cryptosystems, an emerging class of public key cryptosystems used in secure Internet protocols, such as IPSec. An issue of partitioning the description between C and VHDL, and the associated trade-offs are studied in detail. End-to-end speed-ups in the range of 895 to 1300 compared to the pure microprocessor execution time are demonstrated.
Most of Block based motion estimation algorithms are based on computing the sum of absolute differences (SAD) between candidate and reference block. In this paper a FPGA design for fast computing of the minimum SAD is...
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ISBN:
(纸本)3540229892
Most of Block based motion estimation algorithms are based on computing the sum of absolute differences (SAD) between candidate and reference block. In this paper a FPGA design for fast computing of the minimum SAD is proposed. thanks to the use of the on-line arithmetic (OLA) two goal are achieved: it is possible to implement a full 16 x 16 macroblock SAD in a single FPGA device and it permits us to speed up the computation by early truncation of the SAD calculation. Reconfigurable devices allows us to change 8 x 8 or 16 x 16 pixels per block models. Comparison with other related works are provided.
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