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检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

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Automated mapping of coarse-grain pipelined applications to FPGA systems 14th

Automated mapping of coarse-grain pipelined applications to ...

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14th international conference on field programmable logic and applications, FPL 2004

作者： Ziegler, Heidi E. USC Department of Computer Engineering Doctoral Thesis United States

ISBN: (纸本)3540229892

Configurable systems offer a unique opportunity to define application-specific architectures. these architectures offer performance advantages, where the use of customized pipelines exploits the inherent parallelism of the application. In this research, we describe a set of program analyses and an implementation that automatically map a sequential and un-annotated C program into a pipelined implementation targeted to an FPGA with multiple external memories. this research describes an automated approach to hardware design space exploration, through a collaboration between parallelizing compiler technology and high-level synthesis tools. In previous work, we described a compiler algorithm that optimizes individual loop nests, expressed in C, to derive an efficient FPGA implementation. In this research, we describe a global optimization strategy that maps multiple loop nests to a coarse-grain pipelined FPGA implementation. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

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FPGA implementation of a neuromimetic cochlea for a bionic bat head 14th

FPGA implementation of a neuromimetic cochlea for a bionic b...

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14th international conference on field programmable logic and applications, FPL 2004

作者： Clarke, Chris Qiang, Lin Peremans, Herbert Hernández, Álvaro University of Bath Department of Electronic and Electrical Engineering BathBA2 7AY United Kingdom University Antwerpen Department of Environment and Technology Management Prinsstraat 13 Antwerpen 1B-2000 Belgium University of Alcalá Department of Electronics Alcalá of HenaresMadrid28806 Spain

ISBN: (纸本)3540229892

the implementation of a neuromimetic bat model is presented in this paper. In particular the use of an FPGA to perform high performance multichannel frequency filtering is described. Since many applications in auditory modelling require implementation of filter banks that model the characteristics of psychophysical signals, the paper focuses on an FPGA implementation of the digital filters in the neuromimetic cochlear. the paper presents an efficient hardware realization of a number of IIR Butterworth bandpass filters. the pipelined parallel filter architecture is implemented on a single Xilinx Virtex II FPGA chip running in real time. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

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A development support system for applications that use dynamically reconfigurable hardware 14th

A development support system for applications that use dynam...

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14th international conference on field programmable logic and applications, FPL 2004

作者： Ferreira, João Canas Matos, José Silva FEUP/DEEC and INESC Porto Rua Dr. Roberto Frias Porto4200-465 Portugal

ISBN: (纸本)3540229892

ReDiFlex is a system that supports the development of applications that use dynamically and partially-reconfigurable hardware. the hardware functionality is specified by the flow of data between mutable operators. the system automatically creates the physical implementation after partitioning the model to fit the hardware constraints;during application execution new computation-dependent partial configurations can be created. ReDiFlex provides run-time support for reconfiguration and data transfer scheduling. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Reconfigurable hardware

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FPGA implementation of a vision-based motion estimation algorithm for an underwater robot 14th

FPGA implementation of a vision-based motion estimation algo...

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14th international conference on field programmable logic and applications, FPL 2004

作者： Ila, Viorela Garcia, Rafael Charot, Francois Batlle, Joan University of Girona C/ L.Santalo s/n Girona17071 Spain IRISA/INRIA Campus de Beaulieu Rennes Cedex35042 France

ISBN: (纸本)3540229892

this paper presents an FPGA implementation for real-time motion estimation of an underwater robot using computer vision. the algorithm searches for correspondences of a given number of interest points for every image acquired by the camera and some previous reference images. In order to minimise the lighting problems, normalised correlation is used as similarity measurement to match corresponding points in different images. the complexity of normalised correlation criteria determined two main parts in our hardware implementation: an array of Processing Elements (PE) and Post Processing Element (PPE). © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

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A hardware implementation of a content based image retrieval algorithm 14th

A hardware implementation of a content based image retrieval...

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14th international conference on field programmable logic and applications, FPL 2004

作者： Skarpathiotis, Constantinos Dimond, K.R. Department of Electronics University of Kent Canterbury KentCT2 7NT United Kingdom

ISBN: (纸本)3540229892

the need for efficient content-based image retrieval has increased tremendously in many application areas such as biomedicine, military, commerce, education, and Web image classification and searching. We present a method where local and global features are extracted. As a global feature, we extract the colour histogram. As local features, we extract prominent regions from the image using a k-means variant and a labeling algorithm. For each region, colour and spatial locations are extracted. Because these algorithms are computationally intensive, a hardware implementation is presented that accelerates the processing of the images. the proposed design is well suited for implementation on an FPGA. the device can be used as an add-on to a Personal Computer (PC). © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

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Using reconfigurable hardware through web services in distributed applications 14th

Using reconfigurable hardware through web services in distri...

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14th international conference on field programmable logic and applications, FPL 2004

作者： Gonzalez, Ivan Sanchez-Pastor, Javier Hernandez-Ardieta, Jorge L. Gomez-Arribas, Francisco J. Martinez, Javier Escuela Politecnica Superior Universidad Autonoma de Madrid Cantoblanco MadridE-28049 Spain

ISBN: (纸本)3540229892

this paper proposes a simple solution to use reconfigurable hardware in the context of distributed applications. the remote access to the reconfigurable resources is carried out through Web Services technology. So it is possible to exploit the synergy of reconfigurable computing and distributed applications. A web service has been developed to remotely use the whole functionality of a reconfigurable platform. An example application has been developed in order to study the advantages and drawbacks of this methodology. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Web services

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Simulation of an ingenious digital controller for a 6/4 pole switched reluctance motor

Simulation of an ingenious digital controller for a 6/4 pole...

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4th international Power Electronics and Motion Control conference (IPEMC 2004)

作者： Vijayan, S Ramprasath, V Paramasivam, S Arumugam, R Anna Univ Dept Elect & Elect Engn Madras 600025 Tamil Nadu India

ISBN: (纸本)7560518699

this paper discusses the process of designing a digital controller for a 6/4 Switched Reluctance Motor (SRM) using VHDL. SRM is gaining importance nowadays as the high RPM of the motor plays a vital role in applications such as hard disk drive motors where high speed is necessary. Designing a controller for such a motor needs the aid of a processor, which has flexibilities in design and high speed in operation. FPGA provides the solution for the above requirement, as it is compact In size and micro programmed In logic. VHDL Is Very high-speed Integrated circuits Hardware Descriptive Language and is used for defining the functionalities of different modules of the controller. By implementing the controller In FPGA, PWM waveforms can be generated from the kit, which is used to drive the gate of the converter circuit. Most of the controllers, which are In use, occupy lot of space and consume a considerable amount of energy. the digital controller presented here has all its algorithms packed in a single chip, which makes the design easy. In this paper both sensor based and indirect control techniques are discussed.

关键词： switched reluctance motor (SRM) PRIM FPGA (field programmable gate array) digital controller and VHDL

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the impact of pipelining on energy per operation in field-programmable gate arrays

The impact of pipelining on energy per operation in field-pr...

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14th international conference on field programmable logic and applications, FPL 2004

作者： Wilton, Steven J. E. Ang, Su-Shin Luk, Wayne Department of Electrical and Computer Eng University of British Columbia VancouverBC Canada Department of Computing Imperial College London United Kingdom

ISBN: (纸本)3540229892

this paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13μm CMOS high density/high speed FPGA (Altera Stratix EP1S40), and a 0.18μm CMOS low-cost FPGA (Xilinx XC2S200). the results are obtained by both measurements and execution of vendor-supplied tools for power estimation. It is found that pipelining can reduce the amount of energy per operation by between 40% and 90%. Further reduction in energy consumption can be achieved by power-aware clustering, although the effect becomes less pronounced for circuits with a large number of pipeline stages. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

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Power-driven design partitioning 14th

Power-driven design partitioning

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14th international conference on field programmable logic and applications, FPL 2004

作者： Mukherjee, Rajarshi Memik, Seda Ogrenci Electrical and Computer Engineering Northwestern University United States

ISBN: (纸本)3540229892

In order to enable efficient integration of FPGAs into cost effective and reliable high-performance systems as well potentially into low power mobile systems, their power efficiency needs to be improved. In this paper, we propose a power management scheme for FPGAs centered on a power-driven partitioning technique. Our power-driven partitioner creates clusters within a design such that within individual clusters, power consumption can be improved via voltage scaling. We tested the effectiveness of our approach on a set of LUT-level benchmark netlists. Further we did constrained placement of the clusters into predefined Vddhigh and Vddlow regions for a single FPGA. Average savings in power consumption with our approach is 48% whereas penalty in channel width and wire length due to constrained placement is 23% and 26% respectively. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

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MemMap-pd: performance driven technology mapping algorithm for FPGAs with embedded memory arrays

MemMap-pd: performance driven technology mapping algorithm f...

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international Symposium on Parallel and Distributed Processing (IPDPS)

作者： A. Manoj Kumar B. Jayaram R. Manimegalai V. Kamakoti Indian Institute of Technology Madras Chennai India

Summary form only given. Modern day field programmable gate arrays (FPGA) include in addition to look-up tables, reasonably big configurable embedded memory blocks (EMB) to cater to the on-chip memory requirements of systems/applications mapped on them. While mapping applications on to such FPGAs, some of the EMBs may be left unused. We present a methodology to utilize such unused EMBs as large look-up tables to map multioutput combinational subcircuits of the application, with depth minimization as the main objective along with area minimization in terms of the number of LUTs used. Depth minimization is an important goal while mapping performance driven circuits. Experimental results show that our proposed methodology, when employed on popular benchmark circuits, leads to up to 14% reduction in depth when compared with the DAG-map algorithm, along with comparable reduction in area.

关键词： field programmable gate arrays Random access memory Table lookup programmable logic arrays System-on-a-chip Circuit synthesis Minimization methods Read-write memory Lattices logic arrays

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