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Simultaneous timing driven clustering and placement for FPGAs

Simultaneous timing driven clustering and placement for FPGA...

引用

14th international conference on field programmable logic and applications, FPL 2004

作者： Chen, Gang Cong, Jason Computer Science Deparment University of California Los AngelesCA90095 United States

ISBN: (纸本)3540229892

Traditional placement algorithms for FPGAs are normally carried out on a fixed clustering solution of a circuit. the impact of clustering on wirelength and delay of the placement solutions is not well quantified. In this paper, we present an algorithm named SCPlace that performs simultaneous clustering and placement to minimize both the total wirelength and longest path delay. We also incorporate a recently proposed path counting-based net weighting scheme [16]. Our algorithm SCPlace consistently outperforms the state-of-the-art FPGA placement flow (T-VPack + VPR) with an average reduction of up to 36% in total wirelength and 31% in longest path delay. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

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Artificial neural networks processor – A hardware implementation using a FPGA 14th

Artificial neural networks processor – A hardware implement...

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14th international conference on field programmable logic and applications, FPL 2004

作者： Ferreira, Pedro Ribeiro, Pedro Antunes, Ana Dias, Fernando Morgado Escola Superior de Tecnologia de Setúbal do Instituto Politécnico de Setúbal Departamento de Engenharia Electrotécnica Campus do IPS Estefanilha Setúbal2914-508 Portugal

ISBN: (纸本)3540229892

Several implementations of Artificial Neural Networks have been reported in scientific papers. Nevertheless, these implementations do not allow the direct use of off-line trained networks because of the much lower precision when compared with the software solutions where they are prepared or modifications in the activation function. In the present work a hardware solution called Artificial Neural Network Processor, using a FPGA, fits the requirements for a direct implementation of Feedforward Neural Networks, because of the high resolution and accurate activation function that were obtained. the resulting hardware solution is tested with data from a real system to confirm that it can correctly implement the models prepared off-line with MATLAB. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

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IP generation for an FPGA-based audio DAC sigma-delta converter

IP generation for an FPGA-based audio DAC sigma-delta conver...

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14th international conference on field programmable logic and applications, FPL 2004

作者： Ludewig, Ralf Soffke, Oliver Zipf, Peter Glesner, Manfred Pun, Kong Pang Tsoi, Kuen Hung Lee, Kin Hong Leong, Philip Institute of Microelectronic Systems Darmstadt University of Technology Germany Department of Computer Science and Engineering Chinese University of Hong Kong Shatin NT Hong Kong

ISBN: (纸本)3540229892

In this paper we describe a parameterizable FPGA-based implementation of a sigma-delta converter used in a 96kHz audio DAC. From specifications of the converter’s input bitwidth and data sampling frequency, VHDL generic parameters are used to automatically generate the required design. the resulting implementation is optimized to use the minimum internal wordlength and number of stages. We prototyped the converter on an FPGA board for verification purposes and the results are presented. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

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An instance-specific hardware algorithm for finding a maximum clique

An instance-specific hardware algorithm for finding a maximu...

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14th international conference on field programmable logic and applications, FPL 2004

作者： Wakabayashi, Shin’Ichi Kikuchi, Kenji Hiroshima City University 3-4-1 Ozuka-higashi Asaminami-ku Hiroshima731-3194 Japan

ISBN: (纸本)3540229892

this paper presents a hardware algorithm for finding a maximum clique of a given graph, and shows experimental results of the proposed algorithm running on an FPGA. the proposed algorithm is constructed according to a given instance of graph, and can find a maximum clique efficiently based on branch and bound search. the proposed algorithm is designed to be implemented on FPGAs, and realizes an efficient branch and bound search with parallel and pipeline processing. Experimental results showed that, compared with the software solver, the proposed algorithm produced a maximum clique in a very shorter running time even if the time for circuit synthesis and configuration of FPGA was taken into account. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

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A configurable multiprocessor and dynamic load balancing for parallel LU factorization

A configurable multiprocessor and dynamic load balancing for...

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international Symposium on Parallel and Distributed Processing (IPDPS)

作者： X. Wang S.G. Ziavras Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark NJ USA

Summary form only given. the exponentially increasing complexity of many scientific applications and the high cost of supercomputing force us to explore new, sustainable, and affordable high-performance computing platforms. Recent significant advances in FPGA technology and the inherent advantages of configurable logic have brought about new research efforts in the configurable computing field: parallel processing on configurable chips. We explore here parallel LU factorization of large sparse block-diagonal-bordered (BDB) matrices on a configurable multiprocessor that we have designed and implemented. A dynamic load balancing strategy is proposed and analyzed. Performance results for IEEE power test systems are provided. Our research provides evidence that configurable logic can be a viable alternative to high-performance scientific computing.

关键词： Load management field programmable gate arrays Sparse matrices Parallel processing Costs Concurrent computing logic Scientific computing Equations Supercomputers

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On optimal irregular switch box designs

On optimal irregular switch box designs

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14th international conference on field programmable logic and applications, FPL 2004

作者： Fan, Hongbing Wu, Yu-Liang Cheung, Chak-Chung Liu, Jiping The University of Lethbridge LethbridgeABT1K 3M4 Canada The Chinese University of Hong Kong Shatin NT Hong Kong Department of Computing Imperial College London United Kingdom

ISBN: (纸本)3540229892

In this paper, we develop a unified theory in analyzing optimal switch box design problems, particularly for the unsolved irregular cases, where different pin counts are allowed on different sides. the results drawn from our system of linear Diophantine equations based formulation turn out to be general. We prove that the divideand-conquer (reduction) design methodology can also be applied to the irregular cases. Namely, an optimal arbitrarily large irregular or regular switch box can be obtained by combining small prime switch boxes, which largely reduces the design complexity. We revise the known VPR router for our experiments and show that the design optimality of switch boxes does pay off. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

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Monte Carlo radiative heat transfer simulation on a reconfigurable computer

Monte Carlo radiative heat transfer simulation on a reconfig...

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14th international conference on field programmable logic and applications, FPL 2004

作者： Gokhale, Maya Frigo, Janette Ahrens, Christine Tripp, Justin L. Minnich, Ron Los Alamos National Laboratory United States

ISBN: (纸本)3540229892

Recently, the appearance of very large (3 – 10M gate) FPGAs with embedded arithmetic units has opened the door to the possibility of floating point computation on these devices. While previous researchers have described peak performance or kernel matrix operations, there is as yet relatively little experience with mapping an application-specific floating point loop onto FPGAs. In this work, we port a supercomputer application benchmark onto Xilinx Virtex II and Virtex II Pro FPGAs and compare performance with three Pentium IV Xeon microprocessors. Our results show that this application-specific pipeline, with 12 multiply, 10 add/subtract, one divide, and two compare modules of single precision floating point data type, shows speed up of 10.37×.We analyze the tradeoffs between hardware and software to characterize the algorithms that will perform well on current and future FPGA architectures. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

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Implementing cellular automata in FPGA logic

Implementing cellular automata in FPGA logic

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international Symposium on Parallel and Distributed Processing (IPDPS)

作者： M. Halbach R. Hoffmann TU Darmstadt FB Informatik Darmstadt Germany

Summary form only given. We have searched for a performance platform to run billions of simulations in the cellular automata model for optimizing applications. the question was how much speed-up could be gained by using the FPGA technology compared to optimized software. We have implemented to cellular automata rules in software on a PC and in hardware. On our low end experimental platform we reached a speed-up of 3 for a medium complex rule and 22 for a complex rule. If we would use the latest high end FPGA technology, speed-ups up to many thousand are realistic. A cluster of thousands of workstations would be necessary to reach the same performance, which is much more costly than the FPGA solution.

关键词： field programmable gate arrays logic Hardware Concurrent computing Software prototyping Biology computing Random access memory Prototypes Electronic mail Application software

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Automating optimized table-with-polynomial function evaluation for FPGAs

Automating optimized table-with-polynomial function evaluati...

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14th international conference on field programmable logic and applications, FPL 2004

作者： Lee, Dong-U Mencer, Oskar Pearce, David J. Luk, Wayne Department of Computing Imperial College London United Kingdom

ISBN: (纸本)3540229892

Function evaluation is at the core of many compute-intensive applications which perform well on reconfigurable ***, in order to implement function evaluation efficiently, the FPGA programmer has to choose between a multitude of function evaluation methods such as table lookup, polynomial approximation, or table lookup combined with polynomial approximation. In this paper, we present a methodology and a partially automated implementation to select the best function evaluation hardware for a given function, accuracy requirement, technology mapping and optimization metrics, such as area, throughput and latency. the automation of function evaluation unit design is combined with ASC,A Stream Compiler, for FPGAs. On the algorithmic side, MATLAB designs approximation algorithms with polynomial coefficients and minimizes bitwidths. On the hardware implementation side, ASC provides partially automated design space exploration. We illustrate our approach for sin(x), log(1+x) and 2x with a selection of graphs that characterize the design space with various dimensions, including accuracy, precision and function evaluation method. We also demonstrate design space exploration by implementing more than 400 distinct designs. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

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A framework for energy efficient design of multi-rate applications using hybrid reconfigurable systems

A framework for energy efficient design of multi-rate applic...

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14th international conference on field programmable logic and applications, FPL 2004

作者： Mohanty, Sumit Prasanna, Viktor K. University of Southern California CA United States

ISBN: (纸本)3540229892

Hybrid reconfigurable systems integrate DSPs and general purpose processors with an FPGA fabric. these systems may support features such as efficient start-up and shut-down, dynamic voltage scaling, and reconfiguration, that are exploited for energy-efficient application design. Duty cycle is the proportion of time during which a system is operated. Multi-rate applications consist of tasks that execute at different rates. Designing an energy-efficient hybrid reconfigurable system with duty cycle specification that implements a multi-rate application using devices with multiple operating states presents several challenges such as modeling, rapid performance estimation, and efficient design space exploration. We present a design framework that addresses these challenges. Using our framework, we illustrate the design of two energy efficient systems: automated target detection and adaptive beamforming. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Voltage scaling

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