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检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

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Comparative study of SRT-dividers in FPGA

Comparative study of SRT-dividers in FPGA

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14th international conference on field programmable logic and applications, FPL 2004

作者： Sutter, Gustavo Bioul, Gery Deschamps, Jean-Pierre School of Engineering Universidad Autonoma de Madrid Spain UNC-Tandil UFASTA-Mar del Plata Argentina Dept. Eng. Electrònica Elèctrica i Automàtica Universitat Rovira i Virgili Tarragona Spain

ISBN: (纸本)3540229892

this paper describes different implementations of dividers on FPGA. Many division algorithms have been adapted for FPGA technology;nevertheless the peculiar characteristics of re-configurable hardware devices deserve special attention to ensure efficient implementations. this paper presents comparative analyses of implementations targeting Virtex and Virtex II FPGA technology. With respect to the algorithms, selected comparison criteria are operand widths, remainder representations and radix options. At the implementation level, latency, throughput, and area consumption have been traded-off within array, pipelined and sequential options;the results have been compared with previous ones. Area and speed improvements have been obtained thanks to careful implementation techniques. With respect to non-restoring implementations, significant delay improvements - up to 42% - have been achieved. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

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Using multi-bit logic blocks and automated packing to improve field-programmable gate array density for implementing datapath circuits

Using multi-bit logic blocks and automated packing to improv...

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IEEE international conference on field-programmable Technology (FPT)

作者： A.G. Ye J. Rose University of Toronto Canada

As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are being increasingly used to implement large arithmetic-intensive applications, which often contain a large proportion of datapath circuits. Since datapath circuits usually consist of regularly structured components, called bit-slices, it is possible to utilize datapath regularity in order to achieve significant area savings through FPGA architectural innovations. this work describes such an FPGA logic block architecture, called a multi-bit logic block, which employs configuration memory sharing to exploit datapath regularity. It is experimentally shown that, comparing to conventional FPGA logic blocks, the multi-bit logic blocks can achieve 18% to 26% logic block area reduction for implementing datapath circuits, which represents an overall FPGA area saving of 5% to 13%. A packing algorithm for the multi-bit logic block architecture is also proposed in this paper; and it is used to empirically find the best values for several important architectural parameters of the new architecture, including the most area efficient granularity values and the most area efficient amount of configuration memory sharing.

关键词： logic arrays logic circuits field programmable gate arrays logic programming Routing logic design Signal processing algorithms logic devices Design automation Technological innovation

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SoftSONIC: A customisable modular platform for video applications

SoftSONIC: A customisable modular platform for video applica...

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14th international conference on field programmable logic and applications, FPL 2004

作者： Rissa, Tero Cheung, Peter Y. K. Luk, Wayne Department of Computing Imperial College London United Kingdom Department of Electrical and Electronic Engineering Imperial College London United Kingdom

ISBN: (纸本)3540229892

this paper presents the Customisable Modular Platform (CMP) approach. the aim is to accelerate FPGA application development by raising the level of abstraction and facilitating design reuse. the solution is based on network of Nodes, communicating using packetbased protocol. the approach is illustrated using SoftSONIC, a CMP for video applications. Our approach promotes modularity and design reuse by having multiple interoperable layers of design abstraction, while supporting advanced development and verification methods such as mixedabstraction execution and efficient system-level simulation based on Transaction Level Modelling. the platform provides domain-specific abstractions and customisations of various elements such as communication protocols and topology, enabling exploitation of data locality and fineand coarse-grain parallelism. the benefits of our approach is demonstrated using SoftSONIC for development of several real-time HDTV video processing applications. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Abstracting

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Scalable and modular algorithms for floating-point matrix multiplication on FPGAs

Scalable and modular algorithms for floating-point matrix mu...

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international Symposium on Parallel and Distributed Processing (IPDPS)

作者： L. Zhuo V.K. Prasanna Department of Electrical Engineering University of Southern California Los Angeles USA

Summary form only given. the abundant hardware resources on current FPGAs provide new opportunities to improve the performance of hardware implementations of scientific computations. We propose two FPGA-based algorithms for floating-point matrix multiplication, a fundamental kernel in a number of scientific applications. We analyze the design tradeoffs in implementing this kernel on FPGAs. Our algorithms employ a linear array architecture with a small control logic. this architecture effectively utilizes the hardware resources on the entire FPGA and reduces the routing complexity. the processing elements (PEs) used in our algorithms are modular so that floating-point units can be easily embedded into them. In our designs, the floating-point units are optimized to maximize the number of PEs integrated on the FPGA as well as the clock speed. Experimental results show that our algorithms achieve high clock speeds and provide good scalability. Our algorithms achieve superior sustained floating-point performance compared with existing FPGA-based implementations and state-of-the-art processors.

关键词： field programmable gate arrays Hardware logic arrays Clocks Algorithm design and analysis Routing logic devices Kernel Computer architecture Floating-point arithmetic

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A methodology for energy efficient FPGA designs using malleable algorithms 14th

A methodology for energy efficient FPGA designs using mallea...

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14th international conference on field programmable logic and applications, FPL 2004

作者： Ou, Jingzhao Prasanna, Viktor K. Department of Electrical Engineering University of Southern California Los AngelesCA90089-2560 United States

ISBN: (纸本)3540229892

A recent trend towards integrating FPGAs with many heterogeneous components, such as memory systems, dedicated multipliers, etc., has made them an attractive option for implementing many embedded systems. Paradoxically, the integration that makes modern FPGAs an attractive computing substrate also makes the development of energy efficient FPGA designs very challenging in practice. this is due to the many alternatives available for implementing a desired functionality and a lack of high-level models of FPGA architectures that can accurately capture the energy dissipation behavior of alternatives. To address these issues, we propose a methodology for energy efficient FPGA designs using malleable algorithms. Malleable algorithms are used to expose the architecture platform aware specifications of alternate implementations of the desired functionalities. Our methodology consists of three major design steps: domain-specific energy performance modeling, development of malleable algorithms, and system level optimization. Energy efficient designs are realized through close interaction among these three design steps. To illustrate the proposed design methodology and demonstrate the benefits of designing using malleable algorithms, we present the development of a beamforming application through a high-levelMAT-LAB/Simulink based FPGA design tool developed by us. By tuning the design knobs exposed by malleable algorithms, the design of the beamforming application identified through system-level optimization achieves up to 30% energy reduction compared with other designs considered in our experiments. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

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On computing maximum likelihood phylogeny using FPGA 14th

On computing maximum likelihood phylogeny using FPGA

引用

14th international conference on field programmable logic and applications, FPL 2004

作者： Mak, Terrence S. T. Lam, K.P. Department of Systems Engineering and Engineering Management The Chinese University of Hong Kong Hong Kong

ISBN: (纸本)3540229892

Phylogenetic tree (or phylogeny) is a meaningful tree representation for the evolutionary history of different organisms that it has been shown useful in drug discovery, virus identification and functional genomic study [1]. the objective of this project is to develop efficient FPGA implementations for phylogenetic tree reconstruction algorithms. By taking advantage of hardware high-performance, we explore the possibilities of parallelization and system optimization to provide high-speed acceleration for the phylogeny inference. the Maximum Likelihood approach for inferring the phylogeny from molecular data has received much attention [2]. Although the optimal ML phylogenetic tree search problem is classified as NP-hard and it is difficult to find the optimal solution, the GAML algorithm (based on Genetic Algorithm and Maximum Likelihood) has been shown to find a good near-optimal solution in reasonable time [3]. In [4], we have shown that using HW/SW (Hardware/ Software) codesign for GAML implementation can provide significant speed-up when compared with software-only implementation. Our HW/SW system has good potential for handling large scale problems in real applications. In [5], an enhanced version of FPGA design with parallel and pipelined implementation for the likelihood evaluation is proposed. It has been shown 100 times faster than the single-CPU solution for the ML tree evaluation. To reduce precision loss attributed to truncation error in the FPGA, we are developing a dynamic floating-point alike structure based on the fixed-point architecture. We have also studied the implementation of phylogenetic tree reconstruction algorithm in the embedded platform (i.e. VirtexII-Pro Platform FPGA). Significant improvement in data transmission rate between hardware and software and higher clock frequency of FPGA have been realized [6]. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

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Power analysis attacks against FPGA implementations of the DES

Power analysis attacks against FPGA implementations of the D...

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14th international conference on field programmable logic and applications, FPL 2004

作者： Standaert, François-Xavier Örs, Sıddıka Berna Quisquater, Jean-Jacques Preneel, Bart UCL Crypto Group Laboratoire de Microélectronique Université Catholique de Louvain Place du Levant 3 Louvain-La-NeuveB-1348 Belgium Katholieke Universiteit Leuven Dept.ESAT/SCD-COSIC Kasteelpark Arenberg 10 Leuven-HeverleeB-3001 Belgium

ISBN: (纸本)3540229892

Cryptosystem designers frequently assume that secret parameters will be manipulated in tamper resistant environments. However, physical implementations can be extremely difficult to control and may result in the unintended leakage of side-channel information. In power analysis attacks, it is assumed that the power consumption is correlated to the data that is being processed. An attacker may therefore recover secret information by simply monitoring the power consumption of a device. Several articles have investigated power attacks in the context of smart card implementations. While FPGAs are becoming increasingly popular for cryptographic applications, there are only a few articles that assess their vulnerability to physical attacks. In this article, we demonstrate the specific properties of FPGAs w.r.t. Differential Power Analysis (DPA). First we emphasize that the original attack by Kocher et al. and the improvements by Brier et al. do not apply directly to FPGAs because their physical behavior differs substantially from that of smart cards. then we generalize the DPA attack to FPGAs and provide strong evidence that FPGA implementations of the Data Encryption Standard (DES) are vulnerable to such attacks. © Springer-Verlag Berlin Heidelberg 2004.

关键词： field programmable gate arrays (FPGA)

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Controlling an electrical motion system by a load instruction decoding algorithm using FPGA

Controlling an electrical motion system by a load instructio...

引用

IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： S. Cooper A. Kuperman R. Rabinovici Department of Electrical and Computer Engineering Ben-Gurion University of the Negev Beersheba Israel

this paper presents a motion control system which employs a load decoder, capable of analyzing the load value and changes, applied to the motor's rotor, decoding them into an instruction set for the controller input. the system is implemented in a field programmable gate array (FPGA) device, which have recently become affordable for implementing complicated motion control algorithms. All motion control logic is implemented in hardware (no software at all) and executes functions by the dedicated hardware logic. In such a case execution time becomes inherently fast and deterministic. this complicates the design, compared to the rather simple solution in software on DSP but offers reduced control system price which is essential for mass production applications. Moreover it can be easily transformed into ASIC for further cost reduction.

关键词： Motion control Control systems Decoding field programmable gate arrays logic devices Hardware Rotors programmable logic arrays Digital signal processing Weight control

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Adding limited reconfigurability to superscalar processors 04

Adding limited reconfigurability to superscalar processors

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international conference on Parallel Architecture and Compilation Techniques (PACT)

作者： M. Epalza P. Ienne D. Mlynek Signal Processing Institute Switzerland Processor Architecture Laboratory Switzerland Swiss Federal Institute of Technology Lausanne Switzerland

ISBN: (纸本)9780769522296

When adding reconfigurability to custom hardware, one must take great care that the reduction in speed due to the reconfigurable logic should not cancel out the gains obtained by reconfiguration. these gains are greatest in very specific and computation-intensive applications, and lessen as the applications become more general and heterogeneous. In the case of superscalar processors, this leads to limiting the amount of reconfigurability to precise changes in existing functional units instead of adding a fully configurable functional unit. We present a detailed study of the modifications necessary in a superscalar processor to allow an FPU to be dynamically reconfigured as several ALUs with a minimal increase in the latency of these functional units. the timing of the FPU's multiplier tree and the decision about reconfiguration are exposed. As there is more than one simple unit involved, this decision is more global than a cycle-by-cycle reconfiguration and must be made for a longer period of time. We discuss possible policies for the dynamic reconfiguration decisions. the results show interesting gains of up to 56% in the best cases, and average gains of 10%, on typical architectures over a wide range of applications.

关键词： Reconfigurable logic field programmable gate arrays Hardware Signal processing Delay Automatic control Switches Computer applications Limiting Timing

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Simulation of an ingenious digital controller for a 6/4 pole switched reluctance motor

Simulation of an ingenious digital controller for a 6/4 pole...

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international conference on Power Electronics and Motion Control (IPEMC)

作者： S. Vijayan V. Ramprasath S. Paramasivam R. Arumugam Department of Electrical and Electronics Engineering Anna university Chennai Tamilnadu India

this paper discusses the process of designing a digital controller for a 6/4 switched reluctance motor (SRM) using VHDL. SRM is gaining importance nowadays as the high RPM of the motor plays a vital role in applications such as hard disk drive motors where high speed is necessary. Designing a controller for such a motor needs the aid of a processor, which has flexibilities in design and high speed in operation. FPGA provides the solution for the above requirement, as it is compact in size and micro programmed in logic. VHDL is very high-speed integrated circuits hardware descriptive language and is used for defining the functionalities of different modules of the controller. By implementing the controller in FPGA, PWM waveforms can be generated from the kit, which is used to drive the gate of the converter circuit. Most of the controllers, which are in use, occupy lot of space and consume a considerable amount of energy. the digital controller presented here has all its algorithms packed in a single chip, which makes the design easy. In this paper both sensor based and indirect control techniques are discussed.

关键词： Digital control Reluctance motors Reluctance machines field programmable gate arrays Process design Hard disks logic High speed integrated circuits Hardware Pulse width modulation

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