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A real-time stereo vision system with FPGA

A real-time stereo vision system with FPGA

引用

13th international conference on field-programmable logic and applications (FPL 2003)

作者： Miyajima, Y Maruyama, T Univ Tsukuba Inst Engn Mech & Syst Tsukuba Ibaraki 3058573 Japan

ISBN: (纸本)3540408223

In this paper, we describe a compact stereo vision system which consists of one off-the-shelf FPGA board with one FPGA. this system supports (1) camera calibration for easy use and for simplifying the circuit, and (2) left-right consistency check for reconstructing correct 3-D geometry from the images taken by the cameras. the performance of the system is limited by the calibration (which is, however, a must for practical use) because only one pixel data can be allowed to read in owing to the calibration. the performance is;however, 20 frame per second (when the size of images is 640 x 480, and 80 frames per second when the size of images is 320 x 240), which is fast enough for practical use such as vision systems for autonomous robots. this high performance can be realized by the recent progress of FPGAs and wide memory access to external RAMs (eight memory banks) on the FPGA board.

关键词： field programmable gate arrays (FPGA)

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Domain-specific reconfigurable array for distributed arithmetic

Domain-specific reconfigurable array for distributed arithme...

引用

13th international conference on field-programmable logic and applications (FPL 2003)

作者： Khawam, S Arslan, T Westall, F Univ Edinburgh Sch Elect & Engn Edinburgh EH9 3JL Midlothian Scotland Inst Syst Level Integrat Livingston EH54 7EG Scotland EPSOM Scotland Design Ctr Livingston EH54 7EG Scotland

ISBN: (纸本)3540408223

Distributed Arithmetic techniques are widely used to implement Sum-of-Products computations such as calculations found in multimedia applications like FIR filtering and Discrete Cosine Transform. this paper presents a flexible, low-power and high throughput array for implementing distributed arithmetic computations. Flexibility is achieved by using an array of elements arranged in an interconnect mesh similar to those employed in conventional FPGA architectures. We provide results which demonstrate a significant reduction in power consumption in addition to improvements in timing and area over standard FPGA architectures.

关键词： embedded reconfigurable array programmable distributed arithmetic FPGA domain specific low-power

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DIGIMOD:: A tool to implement FPGA-based digital IF and baseband modems

DIGIMOD:: A tool to implement FPGA-based digital IF and base...

引用

13th international conference on field-programmable logic and applications (FPL 2003)

作者： Marín-Roig, J Torres, V Canet, MJ Pérez, A Sansaloni, T Cardells, F Angarita, F Vicedo, F Almenar, V Valls, J Univ Politecn Valencia Dept Ingn Elect Gandia Spain Univ Politecn Valencia Dept Commun Gandia Spain Hewlett Packard Corp R&D Lab Inkjet Commercial Div Barcelona Spain Univ Miguel Hernandez Dept Fis & Arquitectura Comp Elche Spain

ISBN: (纸本)3540408223

this paper presents a software tool to design intermediate frequency and baseband digital transceivers on FPGA. Main characteristic of this tool is that an ad-hoc interpolation or decimation filter chain composed by CIC, polyphase, pulse shaping, matched filters and a CORDIC-based or ROM-based mixer can be selected. the tool allows the software radio designer to develop downconverters and upconverters and, finally, automatically to generate the VHDL code to implement the system on Xilinx FPGAs.

关键词： field programmable gate arrays (FPGA)

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A high speed computation system for 3D FCHC lattice gas model with FPGA

A high speed computation system for 3D FCHC lattice gas mode...

引用

13th international conference on field-programmable logic and applications (FPL 2003)

作者： Kobori, T Maruyama, T Univ Tsukuba Inst Engn Mech & Syst Tsukuba Ibaraki 3058573 Japan

ISBN: (纸本)3540408223

In this paper, we describe a new computation method for 3D FCHC lattice gas model with FPGA. FCHC lattice gas model is a class of 3D cellular automata and used for simulating fluid dynamics. Many approaches with FPGAs for cellular automata have been researched to date. However, practical three dimensional cellular automata such as an FCHC lattice gas model could not be processed efficiently because they required large size data for each cell and very complex update rules for computing cells. We implemented the new method on an FPGA board with one XC2V6000. the speed gain for FCHC lattice gas model with 128 x 128 x 128 lattice is about 200 times compared with Athlon processor 1800 MHz.

关键词： field programmable gate arrays (FPGA)

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From algorithm graph specification to automatic synthesis of FPGA circuit: a seamless flow of graphs transformations

From algorithm graph specification to automatic synthesis of...

引用

13th international conference on field-programmable logic and applications (FPL 2003)

作者： Kaouane, L Akil, M Sorel, Y Grandpierre, T Lab A2SI Grp ESIEE F-93162 Noisy Le Grand France Inst Natl Rech Informat & Automat OSTRE F-78153 Le Chesnay France

ISBN: (纸本)3540408223

the control, signal and image processing applications are complex in terms of algorithms, hardware architectures and real-time/embedded constraints. System level CAD softwares are then useful to help the designer for prototyping and optimizing such applications. these tools axe oftently based on design flow methodologies. this paper presents a seamless design flow which transforms a data dependence graph specifying the application into an implementation graph containing both data and control paths. the proposed approach follows a set of rules based on the RTL model and on mechanisms of synchronized data transfers in order to transform automatically the initial algorithmic graph into the implementation graph. this transformation flow is part of the extension of our AAA (Algorithm-Architecture Adequation) rapid prototyping methodology to support the optimized implementation of real-time applications on reconfigurable circuits. It has been implemented in SynDEx(1), a system level CAD software tool that supports AAA.

关键词： field programmable gate arrays (FPGA)

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Fast, large-scale string match for a 10Gbps FPGA-based network Intrusion Detection System

Fast, large-scale string match for a 10Gbps FPGA-based netwo...

引用

13th international conference on field-programmable logic and applications (FPL 2003)

作者： Sourdis, I Pnevmatikatos, D Tech Univ Crete Dept Elect & Comp Engn Microprocessor & Hardware Lab GR-73100 Khania Greece Fdn Res & Technol Hellas Inst Comp Sci GR-71110 Iraklion Greece

ISBN: (纸本)3540408223

Intrusion Detection Systems such as Snort scan incoming packets for evidence of security threats. the most computation-intensive part of these systems is a text search against hundreds of patterns, and must be performed at wire-speed. FPGAs are particularly well suited for this task and several such systems have been proposed. In this paper we expand on previous work, in order to achieve and exceed a processing bandwidth of 11Gbps. We employ a scalable, low-latency architecture, and use extensive fine-grain pipelining to tackle the fan-out, match, and encode bottlenecks and achieve operating frequencies in excess of 340MHz for fast Virtex devices. To increase throughput, we use multiple comparators and allow for parallel matching of multiple search strings.. We evaluate the area and latency cost of our approach and find that the match cost per search pattern character is between 4 and 5 logic cells.

关键词： field programmable gate arrays (FPGA)

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An FPGA-based image connected component labeller

An FPGA-based image connected component labeller

引用

13th international conference on field-programmable logic and applications (FPL 2003)

作者： Benkrid, K Sukhsawas, S Crookes, D Benkrid, A Queens Univ Belfast Sch Comp Sci Belfast BT7 1NN Antrim North Ireland

ISBN: (纸本)3540408223

this paper describes an FPGA implementation of a Connected Component Labelling algorithm (CCL), developed at Queen's University Belfast. the algorithm iteratively scans the input image, performing a non-zero maximum neighbourhood operation. It has been coded in Handel C language and targeted Celoxica RC1000-PP PCI board. the whole design was fully implemented and tested on real hardware in less than 24 man-hour. It uses a Virtex-E FPGA and two banks of off-chip memory. For 1024x1024 input images, the whole circuit consumes 583 FPGA slices and 5 Block RAMs and can run at 72 MHz, leading to a 68 pass/sec performance. the FPGA implementation outperforms, easily, an equivalent software implementation running on a 1.6 GHz Pentium-IV PC. A 10-fold speed up has been realised in many instances.

关键词： field programmable gate arrays (FPGA)

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Design and implementation of priority queuing mechanism on FPGA using concurrent periodic EFSMs and parametric model checking

Design and implementation of priority queuing mechanism on F...

引用

13th international conference on field-programmable logic and applications (FPL 2003)

作者： Kitani, T Takamoto, Y Naka, I Yasumoto, K Nakata, A Higashino, T Osaka Univ Grad Sch Informat Sci & Technol Osaka Japan Osaka Seikei Univ Dept Tourism Osaka Japan Nara Inst Sci & Technol Grad Sch Informat Sci Nara 63001 Japan

ISBN: (纸本)3540408223

In this paper, we propose a design and implementation method for priority queuing mechanisms on FPGAs. First, we describe behavior of WFQ (weighted fair queuing) with several parameters in a model called concurrent periodic EFSMs. then, we derive a parameter condition for the concurrent EFSMs to execute their transitions without deadlocks in the specified time period repeatedly under the specified temporal constraints, using parametric model checking technique. From the derived parameter condition, we can decide adequate parameter values satisfying the condition, considering total costs of components. Based on the proposed method, high-reliable and high-performance WFQ circuits for gigabit networks can be synthesized on FPGAs.

关键词： field programmable gate arrays (FPGA)

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Efficient modular-pipelined AES implementation in counter mode on ALTERA FPGA

Efficient modular-pipelined AES implementation in counter mo...

引用

13th international conference on field-programmable logic and applications (FPL 2003)

作者： Charot, F Yahya, E Wagner, C Inst Natl Rech Informat & Automat IRISA F-35042 Rennes France Inst Informat Technol Benha High Inst Technol Banha Egypt

ISBN: (纸本)3540408223

this paper describes a high performance single-chip FPGA implementation of the new Advanced Encryption Standard (AES) algorithm dealing with 128-bit data/key blocks and operating in Counter (CTR) mode. Counter mode has a proven-tight security and it enables the simultaneous processing of multiple blocks without losing the feedback mode advantages. It also gives the advantage of allowing the use of similar hardware for both encryption and decryption parts. the proposed architecture is modular. the architecture basic module implements a single round of the algorithm with the required expansion hardware and control signals. It gives very high flexibility in choosing the degree of pipelining according to the throughput requirements and hardware limitations and this gives the ability to achieve the best compromised design due to these aspects. the FPGA implementation presented is that of a pipelined single chip Rijndael design which runs at a rate of 10.8 Gbits/sec for full pipelining on an ALTERA APEX-EP20KE platform.

关键词： field programmable gate arrays (FPGA)

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Testable clock routing architecture for field programmable gate arrays

Testable clock routing architecture for field programmable g...

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13th international conference on field-programmable logic and applications, FPL 2003

作者： Kalyan Kumar, L. Mupid, Amol J. Ramani, Aditya S. Kamakoti, V. Department of Computer Science and Engineering Indian Institute of Technology ChennaiTamilnadu600036 India

ISBN: (纸本)3540408223

this paper describes an efficient methodology for testing dedicated clock lines in field programmable Gate Arrays (FPGAs). A H-tree based clocking architecture is proposed along with a test scheme. the H-tree architecture provides optimal clock skew characteristics. the H-tree architecture consumes at least 25% less of the routing resources when compared to conventional clock routing schemes. A testing scheme, which utilizes the partial reconfiguration capabilities of FPGAs through selective re-programming of the Complex logic Blocks, to detect and locate faults in the clock lines is proposed. © Springer-Verlag Berlin Heidelberg 2003.

关键词： field programmable gate arrays (FPGA)

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