this paper proposes a real-time bioinspired visual encoding system for multielectrodes’ stimulation of the visual cortex supported on fieldprogrammablelogic. this system includes the spatio-temporal preprocessing s...
详细信息
this paper introduces the Multi-Micro Processor-Array (MMPA) as a kind of Evolvable Hardware (EHW) for an industry control system. At first it describes one of the traditional methods, logic method, for the reconfigur...
详细信息
ISBN:
(纸本)0769519571
this paper introduces the Multi-Micro Processor-Array (MMPA) as a kind of Evolvable Hardware (EHW) for an industry control system. At first it describes one of the traditional methods, logic method, for the reconfiguration of a system. then it applies an evolutionary algorithm to improve the reconfiguration so that the architecture of the control system can be configured dynamically and optimally. the evolutionary algorithm is executed in the structure of the MMPA. Relationship among the components and tasks is employed to speed up searching solutions. Physically the bus connects the microprocessors that form an array. logically the microprocessors construct a ring: Token Ring. the microprocessor that gets the token can send message to any other microprocessor. Each microprocessor stores overall data so when it gets the token it can reconfigure the whole system if necessary.
A self-reconfiguring platform is reported that enables an FPGA to dynamically reconfigure itself under the control of an embedded microprocessor. this platform has been implemented on Xilinx Virtex IItm and Virtex II ...
详细信息
Globally Asynchronous Locally Synchronous (GALS) Systems have provoked renewed interest over recent years as they have the potential to combine the benefits of asynchronous and synchronous design paradigms. It has bee...
详细信息
In Run Time Reconfiguration (RTR) systems, the amount of reconfiguration is considerable when compared to the circuit changes implemented. this is because reconfiguration is not considered as part of the design flow. ...
详细信息
this paper describes a Reconfigurable Hybrid Architecture for the developing, distribution and execution of web applications with high computational requirements. the Architecture is a layered model based on a hybrid ...
详细信息
this paper describes the implementation of the L3 maze routing accelerator in an FPGA. L3 supports fast single-layer and multi-layer routing, preferential routing, and rip-up-and-reroute. A 16 × 16 single-layer a...
详细信息
this paper describes a new efficient multiplier for FPGA-based variable precision processors. the circuit here proposed can adapt itself at runtime to different data wordlengths avoiding time and power consuming recon...
详细信息
In this paper, we describe a computer cache memory simulation environment based on a custom board with multiple FPGAs and DRAM DIMMs. this simulation environment is used for future memory hierarchy evaluation of eithe...
详细信息
this paper presents an improved Xilinx XC6200 FPGA using IBM SiGe BiCMOS technology. the basic cell performance is greatly enhanced by eliminating redundant signal multiplexing procedures. the simulated combinational ...
详细信息
暂无评论