the speed at which a design could be tested (executed) really determines the use of FPGAs for rapid prototying. FPGAs provide reasonable routing resources, and a high capacity for mapping large hardware designs. Howev...
ISBN:
(纸本)3540424997
the speed at which a design could be tested (executed) really determines the use of FPGAs for rapid prototying. FPGAs provide reasonable routing resources, and a high capacity for mapping large hardware designs. However, profitable mapping of computations onto FPGAs is a complex task due to many tradeoffs involved. We present an approach to customize FPGA-based co-processors to most profitably execute loops to speed-up the the execution. Our framework specifically addresses the issues of parallelism, reducing data transfer overheads through reuse, and optimizing the safe frequency at which design can be maximally clocked.
Constant coefficient multiplication using look-up tables is a popular form of multiplication in FPGAs. the ample look-up table resources found within the FPGA match well to the architecture of a look-up table based mu...
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this paper describes the successful implementation of a hardware demonstrator for real-time JPEG standard colour image compression and decompression at picture refresh rates up to 25 frames per second using an FPGA-ce...
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We describe a static profiling methodology to extract hotspots from netlists. Hot-spots are small regular sub-circuits the optimization of which has a big impact on the final result. We have built a tool that can extr...
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With increasing FPGA device capacity and design sizes, physical design closure is becoming more difficult, usually requiring multiple lengthy cycles of placement and routing. Increasing demands are being placed upon t...
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Over the last decade, a large effort has gone into researching the use of FPGA devices for co-processing. Much of the emphasis of this work has been in the area of design entry tools. As FPGA co-processing moves into ...
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We present results on the application of a new methodology based on Parallel and Distributed Genetic Programming (PADGP). the aim for the methodology we present is to automatically perform the placement and routing of...
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the proceedings contain 29 papers. the special focus in this conference is on Evolutionary Design of Electronic Circuits and Embryonic Electronics. the topics include: Two-step incremental evolution of a prosthetic ha...
ISBN:
(纸本)354042671X
the proceedings contain 29 papers. the special focus in this conference is on Evolutionary Design of Electronic Circuits and Embryonic Electronics. the topics include: Two-step incremental evolution of a prosthetic hand controller based on digital logic gates;evolutionary design calibration;implementation of a gate-level evolvable hardware chip;a VLSI implementation of an analog neural network suited for genetic algorithms;initial studies of a new VLSI fieldprogrammable transistor array;an embryonics implementation of a self-replicating universal turing machine;asynchronous embryonics with reconfiguration;artificial cells driven by artificial DNA;a self-repairing and self-healing electronic watch;shrinking the genotype;multi-layered defence mechanisms;human-like dynamic walking for a biped robot using genetic algorithm;effect of fitness for the evolution of autonomous robots in an open-environment;incremental evolution of autonomous robots for a complex task;multi-agent robot learning by means of genetic programming;placing and routing circuits on FPGAs by means of parallel and distributed genetic programming;a massively parallel architecture for linear machine code genetic programming;self-organized evolutionary process in sets of interdependent variables near the midpoint of phase transition in k-satisfiability;evolutionary optimization of yagi-uda antennas;extraction of design patterns from evolutionary algorithms using case-based reasoning;solving partially observable problems by evolution and learning of finite state machines;polymorphic electronics;initial experiments of reconfigurable sensor adapted by evolution;a lossless compression method for halftone images using evolvable hardware and evolvable optical systems and their applications.
the algorithm of test generation based on faults lists cubic cover (FLCC) and single logical path sensitization is offered. the realization of the algorithm is oriented to field Programable Gate Arrays (FPGAs) up to 2...
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the algorithm of test generation based on faults lists cubic cover (FLCC) and single logical path sensitization is offered. the realization of the algorithm is oriented to field Programable Gate Arrays (FPGAs) up to 200000 gates, including more than 20 types of trigger structures. the projects language description - VHDL, supports the design systems of corporations Aldec and Xilinx.
Modern signal processing applications and other compute intensive algorithms can be implemented in fixed ASIC logic to improve performance. the drawback of doing so is that the design is forever fixed with a standard,...
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Modern signal processing applications and other compute intensive algorithms can be implemented in fixed ASIC logic to improve performance. the drawback of doing so is that the design is forever fixed with a standard, protocol or algorithm. the availability of embeddable FPGA cells in ASIC systems allows the designer to set the algorithm in 'reprogrammable' logic. Further, the embedded Liquidlogic core (LL) architecture from LSI logic, provides the ability to manipulate the implemented algorithm at run-time allowing the design to adapt the function in real-time. this paper presents a theoretical ASIC design that utilizes these capabilities and describes dependencies for developing a class of SoC devices.
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