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An embedded programmable core for the implementation of high performance digital filters

An embedded programmable core for the implementation of high...

引用

Annual IEEE international ASIC/SOC conference

作者： B.I. Hounsell T. Arslan Department of Electrical Engineering University of Edinburgh Edinburgh UK

this paper presents a novel, embedded programmable logic array (PLA) for implementing high performance filter functions. A custom-built configurable architecture together with a fast and local interconnect hierarchy, provides a high degree of flexibility for realisation of a given filter specification. the PLA is designed to be reconfigured with external hardware or software all in a system-on-chip platform. A stochastic algorithm is used in this paper to demonstrate the automated configuration of the PLA architecture for a practical filter example. the highly parallel nature of the PLA architecture ensures scalability for complex filter tasks, and provides a highly fault tolerant platform for embedded filter applications. Investigations show that even when 20% of the PLA architecture is damaged the same filter example can still be successfully implemented. Further results demonstrate the scalability, speed, and array utilisation of the architecture using a typical SoC bus specification.

关键词： Digital filters Finite impulse response filter programmable logic arrays Computer architecture Digital signal processing Hardware Scalability System-on-a-chip Stochastic processes field programmable gate arrays

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A novel configurable analog unit architecture

A novel configurable analog unit architecture

引用

international conference on ASIC

作者： Binlin Guo Feng Zhou Jiarong Tong ASIC & System State Key Laboratory Microelectronics Department Fudan University Shanghai China

In this paper, a new architecture of configurable analog unit based on switch capacitor technology is presented. the architecture consists of four parts of input expansion, SC building block, self-calibrating OpAmp and clock control. the architecture not only achieves linear analog application such as integrator, gain amplifier, filter, etc., but also can be expediently configured to implementing some nonlinear analog applications. A programming mechanism using two programmable selector for parameter selector and function selector are illustrated for the architecture. the architecture is propitious to utilize configuration and technology mapping. As nonlinear analog application, a voltage control oscillator is implemented. Simulation result with HSPICE shows that for 0.6 /spl mu/ CMOS process, the relative error of voltage-frequency is less than 0.2%.

关键词： Clocks field programmable analog arrays Switches CMOS technology Functional programming CMOS process Voltage field programmable gate arrays logic Capacitors

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VLSI Reed Solomon decoder architecture for networked multimedia applications

VLSI Reed Solomon decoder architecture for networked multime...

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Annual IEEE international ASIC/SOC conference

作者： M. Martina G. Masera G. Piccinini F. Vacca M. Zamboni Dipartimento di Elettronica Politecnico di Torin Italy

In this paper a novel VLSI Reed Solomon decoder architecture is presented. During the design flow, particular care has been posed to the methodology used in order to grant a great degree of reusability. the obtained decoder core is very suitable for complex System On Chip (SoC) based applications, common in networking environments. In fact, thanks to the high reliability allowed by advanced channel coding techniques, the architecture developed has interesting figures of simplicity and speed. logic synthesis on a FPGA device has shown an operating frequency up to 86 MHz with a core area of just 447 cells.

关键词： Very large scale integration Reed-Solomon codes Decoding System-on-a-chip Channel coding Error correction codes Error correction logic Network synthesis field programmable gate arrays

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In-system reconfiguring and I2C controlling of FPGA based applications

In-system reconfiguring and I2C controlling of FPGA based ap...

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international conference on CAD Systems in Microelectronics (CADSM)

作者： T. Szymanski R. Kielbik A. Napieralski Department of Microelectronics and Computer Science Technical University of Lodz Lodz Poland

In recent years more and more applications are built on FPGA technology supported by additional analog-digital and digital-analog circuits like video processors or RAM-DAC modules. Configuring of reprogrammable circuits is made by special bitstream loading. Additional circuits in most cases are controlled by a two-wire I/sup 2/C bus. In this paper an in-system reconfiguring and I/sup 2/C control concept without extra hardware is described.

关键词： field programmable gate arrays logic Registers Clocks Application software Electronic design automation and methodology Microelectronics Automatic control Integrated circuit interconnections Hard disks

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Genetic tuned FPGA based PD fuzzy LUT controller

Genetic tuned FPGA based PD fuzzy LUT controller

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IEEE international conference on Fuzzy Systems (FUZZ-IEEE)

作者： J.E. Bonilla V.H. Grisales M.A. Melgarejo Programmable Logic applications Group ( GILP ) Universidad Distrital FJDC Bogota Colombia Control and instrumentation applications Group ( GIDIC ) Universidad Distrital FJDC Bogota Colombia

this paper presents the development of an FPGA-based proportional-differential (PD) fuzzy look-up table (LUT) controller. the fuzzy inference uses a 256-value LUT. this method has been used due to its reduced computation time cost. the controller architecture is focused on the treatment of errors and changes in errors with tuning gains in order to regulate the control system dynamics using a traditional method in industrial processes. the controller has been probed with several nonlinear plants, like an inverted pendulum and magnetic levitation, but the tuning of the system is too difficult using an iterative modification of the gains. A genetic algorithm was therefore used as a tuning tool to obtain a particular overshoot in the transient response of the control system.

关键词： Genetics field programmable gate arrays PD control Fuzzy control Table lookup Control systems Error correction Proportional control Computational efficiency Computer architecture

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Testing FPGA based reconfigurable system within run time applications

Testing FPGA based reconfigurable system within run time app...

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international conference on Microelectronics, ICM

作者： A. Doumar H. Ito Computer Laboratory University of Cambridge UK Department of Information and Image Sciences Chiba University Japan

ISBN: (纸本)078037522X

We introduce a technique for testing partially reconfigurable FPGAs. the test technique is intended to be applied in reconfigurable systems in run time applications. Normally, in reconfigurable systems, each FPGA executes many tasks sequentially. therefore, it is configured many times in run time applications. We propose that each FPGA is tested just before each configuration. the whole system remains functional because other FPGAs are still in function when the target FPGA is under test. Since the FPGA's transit time from one task to another has a direct consequence on the system delay, the test must be very fast. therefore, the test proposed targets only a test of tiles where the majority of the data will be configured and only configurable logic blocks actually used are tested. the technique proposed targets test which is achieved within the fault tolerant system, and is very useful in some critical applications with time and resources constraints.

关键词： System testing field programmable gate arrays Application software Hardware logic testing Fault tolerant systems EPROM Laboratories Delay systems Delay effects

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10th international conference on field-programmable logic and applications, FPL 2000

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10th international conference on field-programmable logic and applications, FPL 2000

ISBN: (纸本)3540678999

the proceedings contain 101 papers. the special focus in this conference is on Network Processors and Prototyping. the topics include: the rising wave of field programmability;tightly integrated design space exploration with spatial and temporal partitioning in SPARCS;a dynamically reconfigurable FPGA-based content addressable memory for internet protocol characterization;a compiler directed approach to hiding configuration latency in chameleon processors;reconfigurable network processors based on field programmable system level integrated circuits;field programmable communication emulation and optimization for embedded system design;FPGA-based emulation;FPGA-based prototyping for product definition;implementation of virtual circuits by means of the FIPSOC devices;static and dynamic reconfigurable designs for a 2D shape-adaptive DCT;a self-reconfigurable gate array architecture;multitasking on FPGA coprocessors;design visualisation for dynamically reconfigurable systems;verification of dynamically reconfigurable logic;design of a fault tolerant FPGA;real-time face detection on a configurable hardware system;multifunctional programmable single-board CAN monitoring module;self-testing of linear segments in user-programmed FPGAs;implementing a fieldbus interface using an FPGA;area-optimized technology mapping for hybrid FPGAs;direct mapping of arbitrary components into LUT-based FPGAs;efficient embedding of partitioned circuits onto multi-FPGA boards;a placement algorithm for FPGA designs with multiple I/O standards;a mapping methodology for code trees onto LUT-based FPGAs;possibilities and limitations of applying evolvable hardware to real-world applications;a co-processor system with a virtex FPGA for evolutionary computation and system design with genetic algorithms.

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programmable system level integration brings system-on-chip design to the desktop 10th

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10th international conference on field-programmable logic and applications, FPL 2000

作者： Lafayette, Guy Lecurieux ATMEL European Marketing Manager - Programmable Logic 2 Allee Maryse Bastie Orlytech Wissous Cedex91781 France

this paper introduces a new family of standard products, called FPSLIC FPSLIC (field programmable System Level Integration Circuits), and associated design tools for programmable SoC. © Springer-Verlag Berlin Hei... 详细信息

ISBN: (纸本)3540678999

关键词： System-on-chip

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Multifunctional programmable single-board CAN monitoring module 10th

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10th international conference on field-programmable logic and applications, FPL 2000

作者： Pfeifer, Petr Department of Measurement Czech Technical University in Prague Technicka 2 Praha 616627 Czech Republic

ISBN: (纸本)3540678999

this paper presents PC-104/CAN design of a programmable singleboard multifunctional card, intended for an access to the CAN controllers from industrial version of the ISA bus (PC/104) and event time-stamping by signal changes from controllers and dedicated ISA signals. this paper shows one of possible solutions in a nearly single-chip design. © Springer-Verlag Berlin Heidelberg 2000.

关键词： Artificial intelligence

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Internet connected FPL 10th

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10th international conference on field-programmable logic and applications, FPL 2000

作者： Fallside, Hamish Smith, Michael J. S. Xilinx Inc 2100 Logic Drive San JoseCA95124 United States University of Hawaii at Manoa 2540 Dole Street HonoluluHI96822 United States

ISBN: (纸本)3540678999

In this paper we explore the design of internet-based systems using field-programmable logic (FPL). We describe results from designing a hardware platform that connects FPL directly to an internet. this hardware platform comprises an FPGA;an Ethernet interface;storage for static and dynamic configuration;and nonvolatile configuration logic. An important feature of our hardware platform design is the implementation of network protocols that allow transfer of both application and configuration data to and from an FPGA across an internet. We provide quantitative comparisons between the implementation of network protocols in programmable logic and implementations using general-purpose processors. © Springer-Verlag Berlin Heidelberg 2000.

关键词： field programmable gate arrays (FPGA)

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