the proceedings contain 130 papers. the topics discussed include: FPGA implementation of low-power split-radix FFT processors;a combination of multi-edge coding and independent coding lines for time-to-digital convers...
ISBN:
(纸本)9783000446450
the proceedings contain 130 papers. the topics discussed include: FPGA implementation of low-power split-radix FFT processors;a combination of multi-edge coding and independent coding lines for time-to-digital conversion;using high-level knowledge to enhance data channels in FPGA streaming systems;hardware conversion of neural networks simulation models for neural processing accelerator implemented as FPGA-based SoC;efficient multi-standard cognitive radios on FPGAs;biomedical image processing and reconstruction with dataflow computing on FPGAs;improve defect tolerance in a cluster of a SRAM-based mesh of cluster FPGA using hardware redundancy;efficient implementation of a single-precision floating-point arithmetic unit on FPGA;a fast and scalable FPGA damage diagnostic service for R3TOS using BIST cloning technique;a soft-core processor for finite field arithmetic with a variable word size accelerator;and ultrasmall: the smallest MIPS soft processor.
the proceedings contain 97 papers. the topics discussed include: using island-style bi-directional intra-CLB routing in low power FPGAs;energy efficient partitioning of dynamic reconfigurable MRAM-FPGAs;automatic supp...
ISBN:
(纸本)9780993428005
the proceedings contain 97 papers. the topics discussed include: using island-style bi-directional intra-CLB routing in low power FPGAs;energy efficient partitioning of dynamic reconfigurable MRAM-FPGAs;automatic support for multi-module parallelism from computational patterns;fine-tuning CLB placement to speed up reconfigurations in NVM-based FPGAs;a technology mapper for depth-constrained FPGA logic cells;parallel feature extraction and heterogeneous object-detection for multi-camera driver assistance systems;generating FPGA accelerators for chemical similarity assessment;7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2;NetFPGA - rapid prototyping of high bandwidth devices in open source;optimizing energy efficient low-swing interconnect for sub-threshold FPGAs;reduction calculater in an FPGA based switching hub for high performance clusters;and serial and parallel interleaved modular multipliers on FPGA platform.
the proceedings contain 135 papers. the topics discussed include: the age of adaptive computing is here;multithreading for logic-centric systems;fast prototyping with co-operation of simulation and emulation;how fast ...
ISBN:
(纸本)3540441085
the proceedings contain 135 papers. the topics discussed include: the age of adaptive computing is here;multithreading for logic-centric systems;fast prototyping with co-operation of simulation and emulation;how fast is rapid FPGA-based prototyping: lessons and challenges from the digital TV design prototyping project;implementing asynchronous circuits on LUT based FPGAs;flexible routing architecture generation for domain-specific reconfigurable subsystems;embedded reconfigurable logic core for DSP applications;FPGA QAM demodulator design;modular, fabric-specific synthesis for programmable architectures;improved functional simulation of dynamically reconfigurable logic;dynamic reconfiguration in mobile systems;automatic partitioning for improved placement and routing in complex programmablelogic devices;and high-level partitioning of digital systems based on dynamically reconfigurable devices.
the proceedings contain 111 papers. the topics discussed include: an FPGA-based transverse multibunch feedback system for diamond light source;control techniques for coupling a coarse-grain reconfigurable array with a...
ISBN:
(纸本)9780769541792
the proceedings contain 111 papers. the topics discussed include: an FPGA-based transverse multibunch feedback system for diamond light source;control techniques for coupling a coarse-grain reconfigurable array with a generic RISC core;exploiting dynamic reconfiguration for FPGA based network intrusion detection systems;a scalable, high-performance motion estimation application for a weakly-programmable FPGA architecture;efficiently generating FPGA configurations through a stack machine;a reconfigurable system based on a parallel and pipelined solution for regular expression matching;automation framework for large-scale regular expression matching on FPGA;parallel hardware implementation of connected component tree computation;high-performance integer factoring with reconfigurable devices;advanced multithreading architecture with hardware based scheduling;and a reconfigurable computing scheduler optimized for multicore systems.
the proceedings contain 109 papers. the topics discussed include: evaluating FPGA clusters under wide ranges of design parameters;a high-performance system-on-chip architecture for direct tracking for SLAM;Taiga: a ne...
ISBN:
(纸本)9789090304281
the proceedings contain 109 papers. the topics discussed include: evaluating FPGA clusters under wide ranges of design parameters;a high-performance system-on-chip architecture for direct tracking for SLAM;Taiga: a new RISC-V soft-processor framework enabling high performance CPU architectural features;a generic high throughput architecture for stream processing;enabling partial reconfiguration and low latency routing using segmented FPGA NOCs;rapid implementation of a partially reconfigurable video system with PYNQ;a partial reconfiguration based microphone array network emulator;a dynamic partial reconfigurable overlay concept for PYNQ;ARMHEX: a hardware extension for DIFT on arm-based SOCs;voltage drop-based fault attacks on FPGAs using valid bitstreams;high throughput AES encryption/decryption with efficient reordering and merging techniques;comparison of hardware and software implementations of selected lightweight block ciphers;one size does not fit all: implementation trade-offs for iterative stencil computations on FPGAs;FPGA-based design of a self-checking TMR voter;accelerator-in-switch: a framework for tightly coupled switching hub and an accelerator with FPGA;stripe: signal selection for runtime power estimation;a programming model and runtime system for approximation-aware heterogeneous computing;Vivado design interface: an export/import capability for Vivado FPGA designs;optimizing streaming stencil time-step designs via FPGA floorplanning;and in-switch approximate processing: delayed tasks management for MapReduce applications.
the proceedings contain 101 papers. the special focus in this conference is on Network Processors and Prototyping. the topics include: the rising wave of field programmability;tightly integrated design space explorati...
ISBN:
(纸本)3540678999
the proceedings contain 101 papers. the special focus in this conference is on Network Processors and Prototyping. the topics include: the rising wave of field programmability;tightly integrated design space exploration with spatial and temporal partitioning in SPARCS;a dynamically reconfigurable FPGA-based content addressable memory for internet protocol characterization;a compiler directed approach to hiding configuration latency in chameleon processors;reconfigurable network processors based on fieldprogrammable system level integrated circuits;fieldprogrammable communication emulation and optimization for embedded system design;FPGA-based emulation;FPGA-based prototyping for product definition;implementation of virtual circuits by means of the FIPSOC devices;static and dynamic reconfigurable designs for a 2D shape-adaptive DCT;a self-reconfigurable gate array architecture;multitasking on FPGA coprocessors;design visualisation for dynamically reconfigurable systems;verification of dynamically reconfigurable logic;design of a fault tolerant FPGA;real-time face detection on a configurable hardware system;multifunctional programmable single-board CAN monitoring module;self-testing of linear segments in user-programmed FPGAs;implementing a fieldbus interface using an FPGA;area-optimized technology mapping for hybrid FPGAs;direct mapping of arbitrary components into LUT-based FPGAs;efficient embedding of partitioned circuits onto multi-FPGA boards;a placement algorithm for FPGA designs with multiple I/O standards;a mapping methodology for code trees onto LUT-based FPGAs;possibilities and limitations of applying evolvable hardware to real-world applications;a co-processor system with a virtex FPGA for evolutionary computation and system design with genetic algorithms.
the proceedings contain 177 papers. the special focus in this conference is on Plenary Keynotes;Organic and Biology Computing;Security and Cryptography;Platform Based Design. the topics include: FPGAs and the Era of F...
ISBN:
(纸本)3540229892
the proceedings contain 177 papers. the special focus in this conference is on Plenary Keynotes;Organic and Biology Computing;Security and Cryptography;Platform Based Design. the topics include: FPGAs and the Era of field Programmability;Reconfigurable Systems Emerge;System-Level Design Tools Can Provide Low Cost Solutions in FPGAs;Hardware Accelerated Novel Protein Identification;Large Scale Protein Sequence Alignment Using FPGA Reprogrammablelogic Devices;A Key Management Architecture for Securing Off-Chip Data Transfers;FPGA Implementation of Biometric Authentication System Based on Hand Geometry;A Customisable Modular Platform for Video applications;Deploying Hardware Platforms for SoC Validation;Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes;Power Analysis Attacks Against FPGA Implementations of the DES;Monte Carlo Radiative Heat Transfer Simulation on a Reconfigurable Computer;Stochastic Simulation for Biochemical Reactions on FPGA;Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures;Interconnecting Heterogeneous Nodes in an Adaptive Computing Machine;Improving FPGA Performance and Area Using an Adaptive logic Module;A Dual-VDD Low Power FPGA Architecture;Simultaneous Timing Driven Clustering and Placement for FPGAs;Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis;Compact Buffered Routing Architecture;On Optimal Irregular Switch Box Designs;An Efficient Alternative to Floating-Point Computation;Comparative Study of SRT-Dividers in FPGA;Second Order Function Approximation Using a Single Multiplication on FPGAs;Efficient Modular Division Implementation and A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management.
the proceedings contain 146 papers. the special focus in this conference is on Communications applications, High Level Design Tools, Reconfigurable Architectures, Cryptographic applications, Place and Route Tools. the...
ISBN:
(纸本)3540408223
the proceedings contain 146 papers. the special focus in this conference is on Communications applications, High Level Design Tools, Reconfigurable Architectures, Cryptographic applications, Place and Route Tools. the topics include: Reconfigurable circuits using hybrid hall effect devices;symbol timing synchronization in FPGA-based software radios;an architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix;inter-processor connection reconfiguration based on dynamic look-ahead control of multiple crossbar switches;FPGA implementations of the RC6 block cipher;orchestrating routing structures to maximize routability;virtualizing hardware with multi-context reconfigurable arrays;a dynamically adaptive switching fabric on a multicontext reconfigurable device;reducing the configuration loading time of a coarse grain multicontext reconfigurable device;design strategies and modified descriptions to optimize cipher FPGA implementations;using partial reconfiguration in cryptographic applications;an implementation comparison of an IDEA encryption cryptosystem on two general-purpose reconfigurable computers;low power coarse-grained reconfigurable instruction set processor;encoded-low swing technique for ultra low power interconnect;building run-time reconfigurable systems from tiles;exploiting redundancy to speedup reconfiguration of an FPGA;efficient modular-pipelined AES implementation in counter mode on ALTERA FPGA;an FPGA-based performance analysis of the unrolling, tiling, and pipelining of the AES algorithm;branch optimisation techniques for hardware compilation;a model for hardware realization of kernel loops;globally asynchronous locally synchronous FPGA architectures and synthesizing on a reconfigurable chip an autonomous robot image processing system.
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