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19th international conference on field programmable logic and applications

作者： Rozic, Vladimir Verbauwhede, Ingrid Katholieke Univ Leuven ESAT SCD COSIC & IBBT B-3001 Louvain Belgium

ISBN: (纸本)9781424438914

Random number generators play an important role in the field of cryptography and security. It is often required that a random number generator consists of digital logic blocks only, so that it can be implemented on reconfigurable platforms. Since randomness cannot be proved by statistical tests there is a need for a provably secure hardware random number generator. In order to provide a proof of security, an experimental investigation of various physical effects on reconfigurable platforms is needed. In this paper we focus on the effect of narrow transitions suppression in the logic gates. the estimation of this effect may be crucial for the validity of the security proof of a RNG design. We explain our views on how experiments on FPGA should be performed and we give description of the measurement setup. We show that up to 98% of the transitions are suppressed in our experimental FPGA setup.

关键词： field programmable gate arrays (FPGA)

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A LOW COST RECONFIGURABLE SOFT PROCESSOR FOR MULTIMEDIA applications: DESIGN SYNthESIS AND PROGRAMMING MODEL

A LOW COST RECONFIGURABLE SOFT PROCESSOR FOR MULTIMEDIA APPL...

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19th international conference on field programmable logic and applications

作者： Chalamalasetti, Sai Rahul Vanderbauwhede, Wim Purohit, Sohan Margala, Martin Univ Massachusetts Lowell MA USA Univ Glasgow Dept Comp Sci Glasgow G12 8QQ Lanark Scotland

ISBN: (纸本)9781424438914

this paper presents an FPGA implementation of a low cost 8bit reconfigurable processor core for media processing applications. the core is optimized to provide all basic arithmetic and logic functions required by the media processing and other domains, as well as to make it easily integrable into a 2D array. this paper presents an investigation of the feasibility of the core as a potential soft processing architecture for FPGA platforms. the core was synthesized on the entire Virtex FPGA family to evaluate its overall performance, scalability and portability. A special feature of the proposed architecture is its simple programming model which allows low level programming. throughput results for popular benchmarks coded using the programming model and cycle accurate simulator are presented.

关键词： field programmable gate arrays (FPGA)

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Demonstration of a Context-Switch Method for Heterogeneous Reconfigurable Systems 26

Demonstration of a Context-Switch Method for Heterogeneous R...

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26th international conference on field-programmable logic and applications (FPL)

作者： Wicaksana, Arief Bourge, Alban Muller, Olivier Rousseau, Frederic Grenoble INP UGA CNRS TIMA Lab 46 Ave Felix Viallet F-38000 Grenoble France

ISBN: (纸本)9782839918442

Nowadays, FPGAs are integrated in high-performance computing systems, servers, or even used as accelerators in System-on-Chip (SoC) platforms. Since the execution is performed in hardware, FPGA gives much higher performance and lower energy consumption compared to most microprocessor-based systems. However, the room to improve FPGA performance still exists, e.g. when it is used by multiple users. In multi-user approaches, FPGA resources are shared between several users. therefore, one must be able to interrupt a running circuit at any given time and continue the task at will. An image of the state of the running circuit (context) is saved during interruption and restored when the execution is continued. the ability to extract and restore the context is known as context-switch. © 2016 EPFL.

关键词： field programmable gate arrays (FPGA)

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A Smart Network Interface Approach for Distributed applications on Xilinx Zynq SoCs 28

A Smart Network Interface Approach for Distributed Applicati...

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28th international conference on field programmable logic and applications (FPL)

作者： Shreejith, Shanker Cooke, Ryan A. Fahmy, Suhaib A. Univ Warwick Sch Engn Coventry W Midlands England

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Networked embedded systems have seen tremendous growth with many more complex critical and non-critical systems exchanging information over networks of various types. At each node, information is processed by the network stack before the application sees the data. Large portions of the stack are in software, resulting in significant and non-deterministic delays. While hybrid compute platforms like the Xilinx Zynq can accelerate processing tasks through offloading to programmable logic, the delays incurred due to connectivity can significantly impact overall application latency. In this paper, we present a smart network interface approach for the Xilinx Zynq platform based on datapath extensions within the otherwise standard Ethernet interface. We show that this approach improves computation offload latency by 24-27% and throughput by 37% for a complex computational kernel.

关键词： Ethernet Network interfaces Hardware Random access memory Software Registers Monitoring

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Tutorial: 65 NM FPGas, a look under the hood technology, features, and applications

Tutorial: 65 NM FPGas, a look under the hood technology, fea...

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16th international conference on field programmable logic and applications

作者： Alfke, Peter Xilinx Inc San Jose CA USA

ISBN: (纸本)9781424403127

this tutorial describes the Why and How of the new 65-nm families of Virtex-5 FPGAs. It describes several aspects of the technology that affect speed, density, and power consumption. the basic device structure and package design have a strong impact on pc-board signal integrity and supply decoupling requirements. Various new or improved features create opportunities for novel applications in digital signal processing, communications, computing and instrumentation. © 2006 IEEE.

关键词： Digital signal processing

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Improved Resource Sharing for FPGA DSP Blocks 26

Improved Resource Sharing for FPGA DSP Blocks

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26th international conference on field-programmable logic and applications (FPL)

作者： Ronak, Bajaj Fahmy, Suhaib A. Nanyang Technol Univ Sch Comp Sci & Engn Singapore Singapore Univ Warwick Sch Engn Coventry W Midlands England

ISBN: (纸本)9782839918442

Sharing multi-cycle hardware blocks like the DSP48E1 primitive in Xilinx FPGAs can result in significant resource savings, but complicates scheduling. For high-throughput, DSP blocks must be pipelined, which results in a high initiation interval (II) for resource shared implementations. In this paper, we propose a resource reduction technique that minimises DSP block usage while also offering improved II over traditional approaches. this is integrated in a high-level tool which takes datapath descriptions in C and generates synthesisable Verilog RTL with different levels of resource sharing. We demonstrate significantly improved throughput compared to traditional resource sharing while achieving resource reduction compared to resource unconstrained and HLS implementations. the approach explores an otherwise infeasible design space between resource unconstrained and traditional resource sharing methods.

关键词： field programmable gate arrays (FPGA)

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Measuring and utilising the correlation between signal connectivity and signal positioning for FPGAs containing multi-bit building blocks

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 2006年第3期153卷 146-156页

作者： Ye, A. Rose, J. Ryerson Univ Dept Elect & Comp Engn Toronto ON M5B 2K3 Canada Univ Toronto Edward S Rogers Sr Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

As the logic capacity of field-programmable gate arrays (FPGAs) increases, there has been a corresponding increase in the variety of FPGA building blocks. From a mere collection of conventional logic blocks, FPGAs can now include digital signal processors, multipliers, multi-bit addressable memory cells and even processor cores. One of the common characteristics of these new building blocks is their multi-bit design, where each block is designed specifically to process several bits of data at a time. this multi-bit processing paradigm is significantly different from the single-bit processing design of the conventional FPGA logic blocks, as it creates differentiation in signals through its bussed structures. Consequently, the correlation between the positions of the signals in buses and the connectivity of these signals is examined. On the basis of correlation measurements, a multi-bit routing architecture is then proposed along with its routing tool. It is experimentally shown that, compared with the conventional routing architectures, the multi-bit architecture requires 6-12% less area to implement. In particular, it needs 27% fewer routing switches to connect its multi-bit blocks to their routing tracks and 18% less configuration memory to store the configuration information.

关键词： ARCHITECTURE Building blocks field programmable gate arrays Network routing Formal logic signals Routing Switch Process design

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Hardware Acceleration of Feature Detection and Description Algorithms on Low-Power Embedded Platforms 26

Hardware Acceleration of Feature Detection and Description A...

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26th international conference on field-programmable logic and applications (FPL)

作者： Ulusel, Onur Picardo, Christopher Harris, Christopher B. Reda, Sherief Bahar, R. Iris Brown Univ Sch Engn Providence RI 02912 USA

ISBN: (纸本)9782839918442

Image features are broadly used in embedded computer vision applications, from object detection and tracking to motion estimation and 3D reconstruction. Efficient feature extraction and description are crucial due to the real-time requirements of such applications over a constant stream of input data. High-speed computation typically comes at the cost of high power dissipation, yet embedded systems are often highly power constrained, making discovery of power-aware solutions especially critical for these systems. In this paper, we present a power and performance evaluation of three low cost feature detection and description algorithms implemented on various embedded systems (embedded CPUs, GPUs and FPGAs). We show that FPGAs in particular offer attractive solutions for both performance and power and describe several design techniques utilized to accelerate feature extraction and description algorithms on low-cost Zynq SoC FPGAs.

关键词： field programmable gate arrays (FPGA)

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sFPGA2-A SCALABLE GALS FPGA ARCHITECTURE AND DESIGN MEthODOLOGY

sFPGA2-A SCALABLE GALS FPGA ARCHITECTURE AND DESIGN METHODOL...

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19th international conference on field programmable logic and applications

作者： Syed, Rizwan Chen, Xiaolei Ha, Yajun Veeravalli, Bharadwaj Natl Univ Singapore Dept Elect & Comp Engn Singapore 117576 Singapore

ISBN: (纸本)9781424438914

the interconnection networks used by current fine grain FPGAs are not scalable for very big array sizes. To address this issue, we apply the GALS (Globally Asynchronous and Locally Synchronous) paradigm to build scalable FPGAs. the logic resources are divided into locally synchronous tiles and asynchronous communications among different tiles. To route the asynchronous communications, we build a serial network-on-chip. Targeting streaming applications, we propose a design flow that maps user applications to our new FPGA architecture. To validate our architecture and design flow, we build an emulation prototype and develop a JPEG baseline encoder as the case study. We have successfully demonstrated the concept and predict a maximum frequency of 224MHz for designs mapping to sFPGA2 architecture.

关键词： field programmable gate arrays (FPGA)

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Memory parallelism using custom array mapping to heterogeneous storage storage structures

Memory parallelism using custom array mapping to heterogeneo...

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16th international conference on field programmable logic and applications

作者： Baradaran, Nastaran Diniz, Pedro C. Univ Southern Calif Inst Informat Sci Marina Del Rey CA 90292 USA

ISBN: (纸本)9781424403127

Configurable architectures offer the unique opportunity of customizing the storage allocation to meet specific applications' needs. In this paper we describe a compiler approach to map the arrays of a loop-based computation to internal memories of a configurable architecture with the objective of minimizing the overall execution time. We present an algorithm that considers the data access patterns of the arrays along the critical path of the computation as well as the available storage and memory bandwidth. We demonstrate experimental results of the application of this approach for a set of kernel codes when targeting a field-programmable Gate-Array (FPGA). the results reveal that our algorithm outperforms naive and custom data layouts for these kernels by an average of 33% and 15% in terms of execution time, while taking into account the available hardware resources.

关键词： field programmable gate arrays (FPGA)

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