FPGAs are widely used to integrate cryptographic primitives, algorithms, and protocols in cryptographic systemson-chip (CrySoC). As a building block of CrySoCs, True Random Number Generators (TRNGs) exploit analog noi...
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ISBN:
(纸本)9782839918442
FPGAs are widely used to integrate cryptographic primitives, algorithms, and protocols in cryptographic systemson-chip (CrySoC). As a building block of CrySoCs, True Random Number Generators (TRNGs) exploit analog noise sources in electronic devices to generate confidential keys, initialization vectors, challenges, nonces, and random masks in cryptographic protocols. TRNGs aimed at cryptographic applications must fulfill the security requirements defined in the German Federal Bureau for Information Security's (BSI) recommendations AIS20/31, which has become a de facto standard in Europe. Many TRNG cores have already been published, only a few of which are suitable for FPGAs and even fewer comply with AIS-20/31. Here we present the results of the implementation of AIS-20/31 compliant TRNG cores in three FPGA families: Xilinx Spartan 6, Altera Cyclone V and Microsemi SmartFusion 2. In addition to common design parameters like area, bit rate and power/energy consumption, we compare and discuss the feasibility of generator cores in different FPGAs and the statistical quality of their output. these results will help designers select the best generator and the device family to match the requirements of the data security application. To ensure reproducibility of the results, the open source VHDL code of all generators adapted to individual families can be downloaded from the dedicated web page.
In the last years FPGAs have become very important for electronic designs - they are very flexible, provide high configurability and allow short turn around times. Especially for Rapid Prototyping (RP) another feature...
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ISBN:
(纸本)9781424403127
In the last years FPGAs have become very important for electronic designs - they are very flexible, provide high configurability and allow short turn around times. Especially for Rapid Prototyping (RP) another feature plays an important rule: the nearly infinite reprogrammability. Now ever, handling these devices in the engineering process is not an easy issue. therefore our approach presents an efficient, flexible and versatile FPGA configuration methodology based on partial bitstream merging at design time.
QR decomposition, especially through the means of Householder transformation, is often used to solve least squares problems. A matrix to be decomposed withthis method is usually very large, often large enough that it...
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ISBN:
(纸本)9781424410590
QR decomposition, especially through the means of Householder transformation, is often used to solve least squares problems. A matrix to be decomposed withthis method is usually very large, often large enough that it is not able to fit into the main memory of a workstation, let alone the internal memory of an FPGA nowadays. Efficient out-of-core algorithms have been developed to address the factorization of large matrices. this paper describes the application of variants of Householder QR decomposition on FPGA-based systems. More specifically, issues on applying out-of-core algorithms to the relatively small internal memory architecture of FPGA's are investigated.
Block matching motion estimation takes a great part of the processing time for video encoding. To accelerate this process is must to reach real time video coding. the best motion vector is obtained by full-search bloc...
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ISBN:
(纸本)9781424403127
Block matching motion estimation takes a great part of the processing time for video encoding. To accelerate this process is must to reach real time video coding. the best motion vector is obtained by full-search block matching algorithm which has to be usually implemented by hardware. In recent years, several FPGA based designs have been proposed since these devices support high number of process elements in parallel mode. In this paper a survey, of recent architectures to perform the full-search block matching algorithm in FPGAs is presented. A further comparison on terms of frames per second reached, hardware cost in CLB slices and system frequency is presented.
Configuration scrubbing is a technique used for repairing Single Event Upsets (SEUs) within the configuration memory of an FPGA. Scrubbing approaches have been developed using hardware external to the FPGA communicati...
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ISBN:
(纸本)9782839918442
Configuration scrubbing is a technique used for repairing Single Event Upsets (SEUs) within the configuration memory of an FPGA. Scrubbing approaches have been developed using hardware external to the FPGA communicating through a configuration port and using hardware within the FPGA by communicating with an internal configuration port (ICAP). More recent FPGAs such as the Xilinx Zynq 7-Series SoCs provide internal programmable processors that can configure the FPGA logic very rapidly using an internal Processor Configuration Access Port (PCAP). these SoC/FPGAs also provide automatic internal scrubbing through the use of high-speed readback and configuration error correction. this paper presents a novel form of FPGA configuration scrubbing for the Zynq-7000 SoC family by combining the highspeed PCAP configuration port with internal scrubbing. this novel scrubber corrects single-bit upsets in several microseconds and detects these upsets in 8 ms.
Understanding how FPGAs age and how to control that aging is crucial for ensuring the reliability and security of FPGAs in critical applications. Due to the proprietary nature of commercial FPGAs, it can be challengin...
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ISBN:
(纸本)9798331530082;9798331530075
Understanding how FPGAs age and how to control that aging is crucial for ensuring the reliability and security of FPGAs in critical applications. Due to the proprietary nature of commercial FPGAs, it can be challenging to validate aging models on real silicon, and most previous work has relied on circuit simulations to study the effects of FPGA aging. In this work, we leverage low-level placement and routing APIs provided by RapidWright to create a series of stressor and characterization circuits that allow us to measure the effects of aging on individual LUTs and routing resources in a 28nm FPGA. We demonstrate how these techniques allow fine-grained control of the relative aging of different FPGA resources, even to the point of aging individual paths within a single LUT. Several different aging experiments are demonstrated, and in a cumulative test, we show how different signal and LUT configurations can influence the aging rate by over 2x.
FPGAs are rising in popularity for acceleration in all kinds of systems. However, even in cloud environments, FPGA devices are typically still used exclusively by one application only. To overcome this, and as an appr...
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ISBN:
(数字)9781538685174
ISBN:
(纸本)9781538685174
FPGAs are rising in popularity for acceleration in all kinds of systems. However, even in cloud environments, FPGA devices are typically still used exclusively by one application only. To overcome this, and as an approach to manage FPGA resources with OS functionality, this paper introduces the concept of resource elastic virtualization which allows shrinking and growing of accelerators in the spatial domain withthe help of partial reconfiguration. Withthis, we can serve multiple applications simultaneously on the same FPGA and optimize the resource utilization and consequently the overall system performance. We demonstrate how an implementation of resource elasticity can be realized for OpenCL accelerators along with how it can achieve 23x better FPGA utilization and 49% better performance on average while simultaneously lowering waiting time for tasks.
A high speed FPGA off-loading engine for detecting the license plate itself in order to avoid the traffic accident is proposed. A complicated algorithm is written in Handel-C, and parallel processing is explicitly uti...
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ISBN:
(纸本)9781424410590
A high speed FPGA off-loading engine for detecting the license plate itself in order to avoid the traffic accident is proposed. A complicated algorithm is written in Handel-C, and parallel processing is explicitly utilized in every level of implementation;an input image is segmented into 16 areas, and each area is processed in parallel by a multiple calculation unit executing pipeline processing and a distributed memory module. A prototype circuit implemented on a general purpose FPGA board achieved 4.16 times performance as software execution on a Pentium-III desktop PC. the highest performance in literature;100 frames per second;can be achieved.
As FPGA technology and related EDA tools develop, design IP protection and licensing requires increasing consideration. the current multi-player, Partial-Reconfiguration (PR) design flow does not facilitate bitstream-...
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ISBN:
(纸本)9781424438914
As FPGA technology and related EDA tools develop, design IP protection and licensing requires increasing consideration. the current multi-player, Partial-Reconfiguration (PR) design flow does not facilitate bitstream-level IP core license enforcement, e.g, time-limited or pay-per-use. this paper proposes the use of a Secure Reconfigurable Controller (SeReCon) for accounting of IP core usage, e.g. total runtime, no. of activations etc, in a PR system. this paper extends the reported SeReCon root-of-trust to support license enforcement within the PR flow and to facilitate confidentiality of the IP core during the PR system life-cycle. A prototype IP-aware SeReCon demonstrator, implemented on Virtex-5 and supporting reconfiguration of a PCIe accelerator with cryptographic IP cores is described.
this paper discusses the need for new high-speed hardware architectures for future networks and in particular the need for high speed, high capacity shared buffer designs. An implementation of such a buffer using FPGA...
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ISBN:
(纸本)9781424410590
this paper discusses the need for new high-speed hardware architectures for future networks and in particular the need for high speed, high capacity shared buffer designs. An implementation of such a buffer using FPGA technology utilizing RLDRAM II is presented. the architecture that has been derived and implemented operated at 12.8Gbps and is scalable up to 20Gbps.
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