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检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

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On-the-Fly Parallel Data Shuffling for Graph Processing on OpenCL-based FPGAs 29

On-The-Fly Parallel Data Shuffling for Graph Processing on O...

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29th international conference on field-programmable logic and applications (FPL)

作者： Chen, Xinyu Bajaj, Ronak Chen, Yao He, Jiong He, Bingsheng Wong, Weng-Fai Chen, Deming Natl Univ Singapore Singapore Singapore Adv Digital Sci Ctr Singapore Singapore Alibaba Grp Hangzhou Peoples R China Univ Illinois Urbana IL 61801 USA

ISBN: (纸本)9781728148847

Graph processing has attracted much attention recently due to its popularity in many big data analytic applications. With high performance and energy efficiency, FPGAs can be an attractive architecture for graph processing. A number of techniques such as caching using block RAMs (BRAMs) to reduce random accesses of global memory and multiple processing element (PE) instances for high throughput have been explored. OpenCL-based FPGAs natively support a high-level programming paradigm, providing good programmability to developers. However, challenges remain because the run-time dependency introduced by multiple PEs usually cannot be handled efficiently by OpenCL's high-level control granularity. In this paper, we propose a novel on-the-fly parallel data shuffling technique that can be implemented in OpenCL to solve this problem. We have integrated our shuffling technique to an edge-centric graph processing framework which achieves a throughput of more than 1,000 million traversed edges per second (MTEPS) on PageRank, SpMV, BFS and SSSP applications and is even better than existing RTL-based designs.

关键词： field programmable gate arrays Parallel processing throughput Hardware Layout Engines Computer architecture

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Security Assessment of Microfluidic Fully-programmable-Valve-Array Biochips 32

Security Assessment of Microfluidic Fully-Programmable-Valve...

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32nd international conference on VLSI Design (VLSID) / 18th international conference on Embedded Systems (ES)

作者： Shayan, Mohammed Bhattacharjee, Sukanta Song, Yong-Ak Chakrabarty, Krishnendu Karri, Ramesh NYU New York NY 10003 USA New York Univ Abu Dhabi Abu Dhabi U Arab Emirates Duke Univ Durham NC 27706 USA

ISBN: (纸本)9781728104096

the fully-programmable-valve-array (FPVA) is a general-purpose programmable flow-based microfluidic platform, akin to the VLSI field-programmable gate array (FPGA). FPVAs are dynamically reconfigurable and hence are suitable in a broad spectrum of applications involving immunoassays and cell analysis. Since these applications are safety-critical, addressing security concerns is vital for the success and adoption of FPVAs. this study evaluates the security of FPVA biochips. We show that FPVAs are vulnerable to malicious operations similar to digital and flow-based microfluidic biochips. FPVAs are further prone to new classes of attacks -tunneling and deliberate aging. the study establishes security metrics and describes possible attacks on real-life bioassays.

关键词： Biochips Valves Security Multiplexing Biological system modeling Pressure sensors

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DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses 29

DynaBurst: Dynamically Assemblying DRAM Bursts over a Multit...

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29th international conference on field-programmable logic and applications (FPL)

作者： Asiatici, Mikhail Ienne, Paolo Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland

ISBN: (纸本)9781728148847

the effective bandwidth of the FPGA external memory, usually DRAM, is extremely sensitive to the access pattern. Nonblocking caches that handle thousands of outstanding misses (miss-optimized memory systems) can dynamically improve bandwidth utilization whenever memory accesses are irregular and application-specific optimizations are not available or are too costly in terms of design time. However, they require a memory controller with wide data ports on the FPGA side and cannot fully take advantage of the memory interfaces with multiple narrow ports that are common on SoC FPGAs. Moreover, as their scope is limited to single memory requests, the access pattern they generate may cause frequent DRAM row conflicts, which further reduce DRAM bandwidth. In this paper, we propose DynaBurst, an extension of miss-optimized memory systems that generates variable-length bursts to the memory controller. By making memory accesses locally more sequential, we minimize the number of DRAM row conflicts, and by adapting the burst length on a per-request basis we minimize bandwidth wastage. On a multiple, narrow-ported DDR3 controller, we provide 28% geometric mean and up to 3.4x speedup compared to a traditional nonblocking cache of the same area, while the prior single-request approach would not have been cost-effective. On a controller with a single, wide port, we can further improve the performance of miss-optimized systems by up to 2.4 x.

关键词： Random access memory Bandwidth field programmable gate arrays Memory management Optimization throughput Registers

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Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack 29

Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack

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29th international conference on field-programmable logic and applications (FPL)

作者： Ruiz, Mario Sidler, David Sutter, Gustavo Alonso, Gustavo Lopez-Buedo, Sergio Univ Autonoma Madrid Escuela Politecn Super High Performance Comp & Networking Res Grp Madrid Spain Swiss Fed Inst Technol Dept Comp Sci Syst Grp Zurich Switzerland NAUDIT HPCN Madrid Spain

ISBN: (纸本)9781728148847

the realization that the network is becoming an important bottleneck in computing clusters and in the cloud has led in the past years to an increase scrutiny of how networking functionality is deployed. From TCP Offload Engines (TOEs) to Software Defined Networking (SDN), including Smart NICs and In-Network Data Processing, a wide range of approaches are currently being explored to increase the efficiency of networks and tailor its functionality to the actual needs of the application at hand. To address the need for an open and customizable networking stack, in this paper we introduce Limago, an FPGA-based open-source implementation of a TCP/IP stack operating at 100 Gbit/s. To our knowledge, Limago provides the first complete description of an FPGA-based TCP/IP stack at these speeds, thereby illustrating the bottlenecks that must be addressed, proposing several innovative designs to reach the necessary throughput, and showing how to incorporate advanced protocol features into the design. As an example, Limago supports the TCP Window Scale option, addressing the Long Fat Pipe issue. Limago not only enables 100 Gbit/s Ethernet links in an open source package, but also paves the way to programmable and fully customizable NICs based on FPGAs.

关键词： TCPIP field programmable gate arrays Microsoft Windows Bandwidth Cloud computing Open source software

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Data stream statistics over sliding windows: How to summarize 150 Million updates per second on a single node 29

Data stream statistics over sliding windows: How to summariz...

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29th international conference on field-programmable logic and applications (FPL)

作者： Chrysos, Grigorios Papapetrou, Odysseas Pnevmatikatos, Dionisios Dollas, Apostolos Garofalakis, Minos Tech Univ Crete Sch Elect & Comp Engn Iraklion Greece Eindhoven Univ Technol Dept Math & Comp Sci Eindhoven Netherlands ATHENA Res & Innovat Ctr Athens Greece

ISBN: (纸本)9781728148847

Traditional data management systems map information using centralized and static data structures. Modern applications need to process in real time datasets much larger than system memory. To achieve this, they use dynamic entities that are updated with streaming input data over a sliding window. For efficient and high performance processing, approximate sketch synopses of input streams have been proposed as effective means for the summarization of streaming data over large sliding windows with probabilistic accuracy guarantees. this work presents a system-level solution to accelerate the Exponential Count-Min (ECM) sketch algorithm on reconfigurable technology. Different reconfigurable architectures for the sketch structure that correspond to different cost and performance tradeoffs are presented. We map the proposed system-level ECM sketch architectures to a high-end modern HPC platform to achieve guaranteed and best-effort update rates up to 150 and 180 million tuples per second respectively. We compare the performance of the implemented system against the best optimized multi-thread software alternative and show that our scalable full-system accelerators outperform software solutions by 5-7.5x for Virtex6 devices and in excess of 10x for current Ultrascale devices.

关键词： Electronic countermeasures Microsoft Windows Complexity theory Histograms field programmable gate arrays IP networks throughput

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Automatic Compiler Based FPGA Accelerator for CNN Training 29

Automatic Compiler Based FPGA Accelerator for CNN Training

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29th international conference on field-programmable logic and applications (FPL)

作者： Venkataramanaiah, Shreyas Kolala Ma, Yufei Yin, Shihui Nurvithadhi, Eriko Dasu, Aravind Cao, Yu Seo, Jae-sun Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85281 USA Intel Corp Intel Labs Hillsboro OR USA Intel Corp Programmable Solut Grp San Jose CA USA

ISBN: (纸本)9781728148847

Training of convolutional neural networks (CNNs) on embedded platforms to support on-device learning is earning vital importance in recent days. Designing flexible training hardware is much more challenging than inference hardware, due to design complexity and large computation/memory requirement. In this work, we present an automatic compiler based FPGA accelerator with 16-bit fixed-point precision for complete CNN training, including Forward Pass (FP), Backward Pass (BP) and Weight Update (WU). We implemented an optimized RTL library to perform training-specific tasks, and developed an RTL compiler to automatically generate FPGA-synthesizable RTL based on user-defined constraints. We present a new cyclic weight storage/access scheme for on-chip BRAM and off-chip DRAM to efficiently implement non-transpose and transpose operations during FP and BP phases, respectively. Representative CNNs for CIFAR-10 dataset are implemented and trained on Intel Stratix 10 GX FPGA using proposed hardware architecture, demonstrating up to 479 GOPS performance.

关键词： Convolution neural networks neural network training back-propagation hardware accelerator FPGA

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Software and Hardware Co-design for Low-Power HPC Platforms 1

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34th international conference on High Performance Computing (ISC High Performance)

作者： Ploumidis, Manolis Kallimanis, Nikolaos D. Asiminakis, Marios Chrysos, Nikos Xirouchakis, Pantelis Gianoudis, Michalis Tzanakis, Leandros Dimou, Nikolaos Psistakis, Antonis Peristerakis, Panagiotis Kalokairinos, Giorgos Papaefstathiou, Vassilis Katevenis, Manolis Fdn Res & Technol Hellas FORTH Iraklion Crete Greece

ISBN: (数字)9783030343569

ISBN: (纸本)9783030343569;9783030343552

In order to keep an HPC cluster viable in terms of economy, serious cost limitations on the hardware and software deployment should be considered, prompting researchers to reconsider the design of modern HPC platforms. In this paper we present a cross-layer communication architecture suitable for emerging HPC platforms based on heterogeneous multiprocessors. We propose simple hardware primitives that enable protected, reliable and virtualized, user-level communication that can easily be integrate in the same package with the processing unit. Using an efficient user-space software stack the proposed architecture provides efficient, low-latency communication mechanisms to HPC applications. Our implementation of the MPI standard that exploits the aforementioned capabilities delivers point-to-point and collective primitives with low overheads, including an eager protocol with end-to-end latency of 1.4 mu s. We port and evaluate our communication stack using real HPC applications in a cluster of 128 ARMv8 processors that are tightly coupled with FPGA logic. the network interface primitives occupy less than 25% of the FPGA logic and only 3 Mbits of SRAM while they can easily saturate the 16 Gb/s links in our platform.

关键词： field programmable gate arrays (FPGA)

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Self-Parameterized Chaotic Map: A Hardware-efficient Scheme Providing Wide Chaotic Range

Self-Parameterized Chaotic Map: A Hardware-efficient Scheme ...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： Partha Sarathi Paul Anurag Dhungel Maisha Sadia Md Razuan Hossain Barry Muldrey Md Sakib Hasan University of Mississippi MS USA

We present a general method called “self-parameterization” for designing one-dimensional (1-D) chaotic maps that provide wider chaotic regions than existing 1-D maps. A wide chaotic range is a desirable property as it strengthens the security feature by enlarging the design space in many hardware-security applications, including reconfigurable logic and encryption. the proposed self-parameterized scheme reduces the hardware cost by involving only one chaotic map that modulates its own control parameter at every iteration by passing the map's previous output through a simple linear transformation. the widening of chaotic range after adding self-parameterization is demonstrated on three classical map functions: logistic, tent, and sine. Two hardware-efficient self-parameterized schemes are presented: one for field-programmable gate array (FPGA) implementation and the other one for integrated circuit (IC) implementation. the chaotic performance of the proposed scheme is evaluated with bifurcation plots and three established chaotic entropy metrics including, Lyapunov exponent, correlation coefficient, and correlation dimension.

关键词： Measurement Reconfigurable logic Bifurcation Hardware Entropy Encryption Security

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Information Metamaterials and Information Systems

Information Metamaterials and Information Systems

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international conference on Infrared and Millimeter Waves

作者： Tie Jun Cui Institute of Electromagnetic Space Southeast University Nanjing China State Key Laboratory of Millimeter Waves Southeast University Nanjing China

Metamaterials have great capabilities and flexibilities in controlling electromagnetic (EM) waves since their subwavelength meta-atoms can be designed and tailored in desired ways. However, once the structure-only metamaterials (i.e., passive metamaterials) are fabricated, their functions will be fixed. To control the EM waves dynamically, some active devices are integrated into the meta-atoms, yielding active metamaterials. Traditionally, the active metamaterials include tunable metamaterials and reconfigurable metamaterials, which have either small-range tunability or a few numbers of reconfigurability. Recently, a special kind of active metamaterials, digital coding and programmable metamaterials, have been presented, which can realize a large number of distinct functionalities and switch them in real time with the aid of field programmable gate array. More importantly, the digital coding representations of metamaterials make it possible to bridge the digital world and physical world using the metamaterial platform, and make the metamaterials process digital information directly, resulting in information metamaterials. In this regard, the information metamaterial is no longer an effective material or medium, but an information system. In this presentation, I will firstly introduce the evolution of metamaterials, and then present the concepts and basic principles of digital coding metamaterials and information metamaterials. With more details, I will introduce a series of information metamaterial systems, including the programmable meta-systems, software meta-systems, and intelligent meta-systems. Particularly, I will present two important applications of the information metamaterials: intelligent computational imaging and wireless communications.

关键词： Wireless communication Imaging Switches logic gates Metamaterials Encoding Software

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A Novel FPGA Architecture of Commentz-Walter Algorithm using Bit-Split String-Matching Engines

A Novel FPGA Architecture of Commentz-Walter Algorithm using...

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international conference on Advances in ICT for Emerging Regions

作者： Sugandima M. Vidanagamachchi Shirley D. Dewasurendra Faculty of Science University of Ruhuna Sri Lanka Faculty of Engineering University of Peradeniya Sri Lanka

ISBN: (纸本)9781665466875

this paper describes a reconfigurable hardware implementation of CommentzWalter algorithm with bit-split string matching engines to match multiple protein sequences. It is reported that multiple pattern matching using the most widely used Aho-Corasick algorithm for different applications has been carried out on graphics processing units and field programmable gate arrays to accelerate the matching process. Commentz-Walter algorithm, is a multiple pattern matching algorithm and more complex than Aho-Corasick. there are no reports of it being directly implemented in any hardware platform except as software implementations on general purpose processors. In this work, a specific architecture for our target application using CommentzWalter algorithm has been developed and tested with a simulator for hardware description languages. this architecture can match multiple patterns of proteins efficiently when implemented on a field programmable Gate Array. Finally, we compare a previously developed hardware architecture of bit-split Aho-Corasick with our bit-split Commentz-Walter architecture. Using the Intel Stratix IV GX EP4SGX230KF40C2 FPGA chip as the target device, the compilation results with Quartus II show that the synthesis logic utilization is 5% with 2203 total number of registers, 64896 FPGA block memory bits and 4 DSP block 18-bit elements. the simulation and practical experimental results show that the proposed architecture can effectively improve the performance of the Commentz-Walter algorithm.

关键词： Proteins Software algorithms Computer architecture logic gates Hardware Software Registers

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