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检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

共 1909 条记录，以下是271-280 订阅

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Automated Extra Pipeline Analysis of applications mapped to Xilinx UltraScale plus FPGAs 26

Automated Extra Pipeline Analysis of Applications mapped to ...

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26th international conference on field-programmable logic and applications (FPL)

作者： Ganusov, Ilya Fraisse, Henri Ng, Aaron Possignolo, Rafael Trapani Das, Sabya Xilinx Inc 2100 Log Dr San Jose CA 95124 USA Univ Calif Santa Cruz Dept Comp Engn Santa Cruz CA 95064 USA

ISBN: (纸本)9782839918442

this paper describes the methodology and algorithms behind extra pipeline analysis tools released in the Xilinx Vivado Design Suite version 2015.3. Extra pipelining is one of the most effective ways to improve performance of FPGA applications. Manual pipelining, however, often requires significant efforts from FPGA designers who need to explore various changes in the RTL and re-run the flow iteratively. the automatic pipelining approach described in this paper, in contrast, allows FPGA users to explore latency vs. performance trade-offs of their designs before investing time and effort into modifying RTL. We describe algorithms behind these tools which use simple cut heuristics to maximize performance improvement while minimizing additional latency and register overhead. To demonstrate the effectiveness of the proposed approach, we analyse a set of 93 commercial FPGA applications and IP blocks mapped to Xilinx UltraScale+ and UltraScale generations of FPGAs. the results show that extra pipelining can provide from 18% to 29% potential Fmax improvement on average. It also shows that the distribution of improvements is bimodal, with almost half of benchmark suite designs showing no improvement due to the presence of large loops. Finally, we demonstrate that highly-pipelined designs map well to UltraScale+ and UltraScale FPGA architectures. Our approach demonstrates 19% and 20% Fmax improvement potential for the UltraScale+ and UltraScale architectures respectively, with the majority of applications reaching their loop limit through pipelining.

关键词： field programmable gate arrays (FPGA)

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On Accelerating Pair-HMM Computations in programmable Hardware 27

On Accelerating Pair-HMM Computations in Programmable Hardwa...

引用

27th international conference on field programmable logic and applications (FPL)

作者： Banerjee, Subho S. el-Hadedy, Mohamed Tan, Ching Y. Kalbarczyk, Zbigniew T. Lumetta, Steve Iyer, Ravishankar K. Univ Illinois Urbana IL 61801 USA

ISBN: (纸本)9789090304281

this paper explores hardware acceleration to significantly improve the runtime of computing the forward algorithm on Pair-HMM models, a crucial step in analyzing mutations in sequenced genomes. We describe 1) the design and evaluation of a novel accelerator architecture that can efficiently process real sequence data without performing wasteful work;and 2) aggressive memoization techniques that can significantly reduce the number of invocations of, and the amount of data transferred to the accelerator. We describe our demonstration of the design on a Xilinx Virtex 7 FPGA in an IBM Power8 system. Our design achieves a 14.85x higher throughput than an 8-core CPU baseline (that uses SIMD and multi-threading) and a 147.49x improvement in throughput per unit of energy expended on the NA12878 sample.

关键词： Coprocessors Reconfigurable architectures Bioinformatics Genomics

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Bent Routing Pattern for FPGA 29

Bent Routing Pattern for FPGA

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29th international conference on field-programmable logic and applications (FPL)

作者： Sun, Xibo Zhou, Hao Wang, Lingli Fudan Univ State Key Lab ASIC & Syst Shanghai Peoples R China

ISBN: (纸本)9781728148847

Routing architecture design is crucial in the early exploration of FPGA fabrics. In the modern unidirectional routing architectures, the signal passes through a programmable switch while turning into the channel perpendicular to the current one at the intersections, which may lead to excessive turning switches in the routing paths and cause the high latency. Most of the researches focus on the routing topology where the wire segments span in either vertical or horizontal direction. In this paper, we propose the bent routing pattern, where the bent wire segments can span in both vertical and horizontal channels without passing through any turning switch. the bent routing topology is designed to keep the regularity and symmetry, and then evaluated by the enhanced VTR. To optimize the architecture with the bent routing pattern, we develop a stochastic searching method based on the simulated annealing algorithm. the results show that the architecture with the mixture of bent wires and straight wires can achieve 9% shorter critical path delay and 11% area-delay product savings on average compared to the architecture with only straight wires.

关键词： Wires Routing Switches field programmable gate arrays Delays Topology Video recording

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Time predictable CPU and DMA shared memory access

Time predictable CPU and DMA shared memory access

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17th international conference on field programmable logic and applications

作者： Pitter, Christof Schoeberl, Martin Vienna Univ Technol Inst Comp Engn Vienna Austria

ISBN: (纸本)9781424410590

In this paper, we propose a first step towards a time predictable computer architecture for single-chip multiprocessing (CMP). CMP is the actual trend in server and desktop systems. CMP is even considered for embedded realtime systems, where worst-case execution time (WCET) estimates are of primary importance. We attack the problem of WCET analysis for several processing units accessing a shared resource (the main memory) by support from the hardware. In this paper, we combine a time predictable Java processor and a direct memory access (DMA) unit with a regular access pattern (VGA controller). We analyze and evaluate different arbitration schemes with respect to schedulability analysis and WCET analysis. We also implement the various combinations in an FPGA. An FPGA is the ideal platform to verify the different concepts and evaluate the results by running applications with industrial background in real hardware.

关键词： field programmable gate arrays (FPGA)

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Characterizing Power Distribution Attacks in Multi-User FPGA Environments 29

Characterizing Power Distribution Attacks in Multi-User FPGA...

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29th international conference on field-programmable logic and applications (FPL)

作者： Provelengios, George Holcomb, Daniel Tessier, Russell Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA

ISBN: (纸本)9781728148847

Multi-tenant FPGAs that contain circuits from multiple users are emerging as a new usage model in cloud and embedded computing environments. Interactions between un-trusting tenant applications in an FPGA can enable new security exposures and the risk of side channel attacks or fault injection. In this work, we investigate the ability for aggressive power consumption of one application to disturb the power network to an extent that causes delay faults in a second application on the same FPGA. In particular, we identify the mechanisms by which the supply voltage is disturbed by the attack, and we characterize the magnitude of the disturbance as a function of time, power consumed by attacker, and position of the victim relative to the attacker. We highlight strategies that can be used to mitigate attacks, including low-cost monitoring circuits that can identify the source of an attack so that the attacker's use of the FPGA can be revoked.

关键词： field programmable gate arrays Voltage measurement Sensors Frequency measurement System-on-chip Cyclones Cloud computing

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Accelerating Low Bit-Width Convolutional Neural Networks With Embedded FPGA 27

Accelerating Low Bit-Width Convolutional Neural Networks Wit...

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27th international conference on field programmable logic and applications (FPL)

作者： Jiao, Li Luo, Cheng Cao, Wei Zhou, Xuegong Wang, Lingli Fudan Univ State Key Lab ASIC & Syst Shanghai Peoples R China

ISBN: (纸本)9789090304281

Convolutional Neural Networks (CNNs) can achieve high classification accuracy while they require complex computation. Binarized Neural Networks (BNNs) with binarized weights and activations can simplify computation but suffer from obvious accuracy loss. In this paper, low bit-width CNNs, BNNs and standard CNNs are compared to show that low bit-width CNNs is better suited for embedded systems. An architecture based on the two-stage arithmetic unit (TSAU) as the basic processing element is proposed to process each layer iteratively for low bit-width CNN accelerators. then the DoReFa-Net which is trained with weights and activations represented in 1 bit and 2 bits respectively is implemented on Zynq XC7Z020 FPGA with a 410.2 GOPS performance. the accelerator can meet the real-time requirement of embedded applications with a 106 FPS throughput and a 73.1% top-5 accuracy on the ImageNet dataset. the accelerator outperforms existing FPGA-based CNN accelerators in the tradeoff among accuracy, energy and resource efficiency.

关键词： Kernel field programmable gate arrays Table lookup Neural networks Computational modeling Quantization (signal) Convolution

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Latency-Driven Design for FPGA-based Convolutional Neural Networks 27

Latency-Driven Design for FPGA-based Convolutional Neural Ne...

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27th international conference on field programmable logic and applications (FPL)

作者： Venieris, Stylianos I. Bouganis, Christos-Savvas Imperial Coll London Dept Elect & Elect Engn London England

ISBN: (纸本)9789090304281

In recent years, Convolutional Neural Networks (ConvNets) have become the quintessential component of several state-of-the-art Artificial Intelligence tasks. Across the spectrum of applications, the performance needs vary significantly, from high-throughput image recognition to the very low-latency requirements of autonomous cars. In this context, FPGAs can provide a potential platform that can be optimally configured based on different performance requirements. However, with the increasing complexity of ConvNet models, the architectural design space becomes overwhelmingly large, asking for principled design flows that address the application-level needs. this paper presents a latency-driven design methodology for mapping ConvNets on FPGAs. the proposed design flow employs novel transformations over a Synchronous Dataflow-based modelling framework together with a latency-centric optimisation procedure in order to efficiently explore the design space targeting low-latency designs. Quantitative evaluation shows large improvements in latency when latency-driven optimisation is in place yielding designs that improve the latency of AlexNet by 73.54x and VGG16 by 5.61x over throughput-optimised designs.

关键词： field programmable gate arrays Feature extraction Space exploration Computational modeling Machine learning Convolution Biological system modeling

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REAPR: Reconfigurable Engine for Automata Processing 27

REAPR: Reconfigurable Engine for Automata Processing

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27th international conference on field programmable logic and applications (FPL)

作者： Xie, Ted Dang, Vinh Wadden, Jack Skadron, Kevin Stan, Mircea Univ Virginia Dept Elect & Comp Engn Charlottesville VA 22903 USA Univ Virginia Dept Comp Sci Charlottesville VA 22903 USA

ISBN: (纸本)9789090304281

Finite automata have proven their usefulness in high-profile domains ranging from network security to machine learning. While prior work focused on their applicability for purely regular expression workloads such as antivirus and network security rulesets, recent research has shown that automata can optimize the performance for algorithms in other areas such as machine learning and even particle physics. Unfortunately, their emulation on traditional CPU architectures is fundamentally slow and further bottlenecked by memory. In this paper, we present REAPR: Reconfigurable Engine for Automata PRocessing, a flexible framework that synthesizes RTL for automata processing applications as well as I/O to handle data transfer to and from the kernel. We show that even with memory and control flow overheads, FPGAs still enable extremely high-throughput computation of automata workloads compared to other architectures.

关键词： Automata field programmable gate arrays Engines Learning automata Benchmark testing Computer architecture

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An Efficient Reconfigurable Architecture by Characterizing Most Frequent logic Functions 25

An Efficient Reconfigurable Architecture by Characterizing M...

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25th international conference on field programmable logic and applications

作者： Ahmadpour, Iman Khaleghi, Behnam Asadi, Hossein Sharif Univ Technol Dept Comp Engn Tehran Iran

ISBN: (纸本)9781467381239

Generous flexibility of Look-Up Tables (LUTs) in implementing arbitrary functions comes with significant performance and area overheads compared with their Application-Specific Integrated Circuit (ASIC) equivalent. One approach to alleviate such overheads is to use less flexible logic elements capable to implement majority of logic functions. In this paper, we first investigate the most frequently used functions in standard benchmarks and then design a set of less-flexible but area-efficient logic cells, called Hard logics (HL). Since higher input functions have diverse classes, we leverage Shannon decomposition to break them into smaller ones to either reduce the HL design space complexity or attain asymmetric low input functions. A heterogeneous LUT-HL architecture and a mapping scheme are also proposed to attain maximum logic resource usage. Experimental results on MCNC benchmarks demonstrate that the proposed architecture reduces area-delay product by 13% and 36% as compared to LUT4 and LUT6 based FPGAs, respectively. Considering the same area budget, our proposed architecture improves performance by 17% and 2% as compared to LUT4 and LUT6 based FPGAs.

关键词： logic functions Formal logic Reconfigurable architectures application specific integrated circuits input function BENCHMARKS Building construction LIPC gene ARCHITECTURE hectolitre

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Versatile Deployment of FPGA Accelerators in Disaggregated Data Centers: a Bioinformatics Case Study 27

Versatile Deployment of FPGA Accelerators in Disaggregated D...

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27th international conference on field programmable logic and applications (FPL)

作者： Alachiotis, Nikolaos theodoropoulos, Dimitris Pnevmatikatos, Dionisios Fdn Res & Technol Hellas Inst Comp Sci Iraklion 70013 Greece Tech Univ Crete Sch Elect & Comp Engn Khania 73100 Greece

ISBN: (纸本)9789090304281

Important design considerations for the cost-effective employment of hardware accelerators in next-generation data centers involve a) the type of candidate applications that a proposed solution can accelerate (generality), and b) the required development effort to successfully deploy the available accelerators for a given application (adoption overhead). To address the problem of generality, we present a versatile and dynamically reconfigurable hardware architecture that exhibits several accelerator slots and programmable interconnect to create application-specific accelerator datapaths. the proposed architecture fits in the model of disaggregated data centers, where compute, memory, and accelerators are broadly regarded as large pools of resources, and subsets of these resource pools are dynamically allocated on an as-needed basis to cooperatively boost performance of a broad range of applications. Initial results for a bioinformatics application that we employ as a case study and deals with the detection of positive selection in large-scale genomic datasets reveal a speedup of up to 6.4X when custom hardware accelerators are mapped to the proposed versatile accelerator architecture and compared with a parallel and highly optimized software implementation executed on a multi-core processor.

关键词： Hardware Acceleration Computer architecture field programmable gate arrays Genomics Bioinformatics

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