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A field programmable Process-In-Memory Architecture Based on RRAM Technology

A Field Programmable Process-In-Memory Architecture Based on...

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international conference on Mechanical, Control and Computer Engineering (ICMCCE)

作者： Yuan Liang Longxiang Yin Ning Xu School of Computer Science and Technology Wuhan University of Technology Wuhan China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China School of Information Engineering Wuhan University of Technology Wuhan China

Conventional reconfigurable architectures, e.g., field-programmable Gate Array (FPGA), are confronted with the inflexibility of the on-chip local memory architecture and the scarce memory resource, which result in the inflexibility to deal with the current memory-thirsty data-intensive applications. Emerging nonvolatile devices, such as resistive random-access memory (RRAM), can operate in a logic-in-memory way, i.e., they can act as both a nonvolatile memory element and a switch, and thus, have the potential to provide higher flexibility and data processing ability. We propose a field-programmable logic-in-memory architecture based on RRAM technology, which is a two-dimensional tile array, where each tile is an RRAM-based crossbar array and can be remolded into three basic modes including logic, interconnect and memory. We further develop a specific adaptive algorithm for placement and routing, which can well exploit the logic-in-memory architecture characteristics. Comparing with traditional FPGAs, our architecture shows 1.9x lower power consumption, 2.8x lower delay, and 5.6x higher performance.

关键词： Nonvolatile memory Computer architecture Switches Routing Delays System-on-chip Reconfigurable architectures

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FPGA Accelerator for Stereo Vision using Semi-Global Matching through Dependency Relaxation

FPGA Accelerator for Stereo Vision using Semi-Global Matchin...

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international conference on field programmable logic and applications

作者： Shashwat Shrivastava Ziaul Choudhury Shashwat Khandelwal Suresh Purini Computer Systems Group International Institute of Information Technology Hyderabad India

ISBN: (数字)9781728199023

ISBN: (纸本)9781728199030

In this paper, we propose a fully parallel and pipelined architecture for stereo vision on FPGAs using Semi-Global Matching with Census Transform being used underneath. Further, we extend the above streaming architecture so that multiple pixels can be processed in a data parallel fashion. We expose this data parallelism through dependency relaxation. this establishes a trade-off between accuracy and throughput of the hardware. We tested the proposed architecture on Virtex-7 FPGA using KITTI 2012 and KITTI 2015 datasets. On images of resolution 1280x960, with 64 disparity levels, we are able to run our hardware design at 100 MHz. At this frequency, our design is able to process 322 frames per second which is 1.6 times faster than the state-of-the-art SGM implementation on FPGA. Our system can be scaled to a higher resolution image.

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Design Patterns for Code Reuse in HLS Packet Processing Pipelines 27

Design Patterns for Code Reuse in HLS Packet Processing Pipe...

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27th IEEE Annual international Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Eran, Haggai Zeno, Lior Istvan, Zsolt Silberstein, Mark Technion Israel Inst Technol Haifa Israel Mellanox Technol Sunnyvale CA USA IMDEA Software Inst Madrid Spain

ISBN: (纸本)9781728111315

High-level synthesis (HLS) allows developers to be more productive in designing FPGA circuits thanks to familiar programming languages and high-level abstractions. In order to create high-performance circuits, HLS tools, such as Xilinx Vivado HLS, require following specific design patterns and techniques. Unfortunately, when applied to network packet processing tasks, these techniques limit code reuse and modularity, requiring developers to use deprecated programming conventions. We propose a methodology for developing high-speed networking applications using Vivado HLS for C++, focusing on reusability, code simplicity, and overall performance. Following this methodology, we implement a class library (ntl) with several building blocks that can be used in a wide spectrum of networking applications. We evaluate the methodology by implementing two applications: a UDP stateless firewall and a key-value store cache designed for FPGA-based SmartNICs, both processing packets at 40Gbps line-rate.

关键词： Optimization Tools C++ languages logic gates Hardware field programmable gate arrays Data structures

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Accelerating human activity recognition systems on FPGAS through a DSL approach 6

Accelerating human activity recognition systems on FPGAS thr...

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6th international Workshop on FPGAs for Software Programmers, FSP 2019, co-located with international conference on field programmable logic and applications, FPL 2019

作者： Fernandes, Daniel A.P.L. Cardoso, João M.P. Faculdade de Engenharia Universidade do Porto Porto Portugal INESC TEC Porto Portugal

ISBN: (纸本)9783800750467

Data analytics is the process of drawing conclusions based on thorough examination of data. It is usually accomplished by machine learning techniques and the algorithms involved must often process large datasets. this severely hurts performance. However, due to the amount of parallel work present in the algorithms, targeting these applications to FPGA-based systems can help in this regard. the problem is the programming model employed by FPGAs. Most software developers have little to no knowledge in hardware description languages (HDLs) and even the currently available high-level synthesis (HLS) tools are difficult to master, as these still require much familiarity with the hardware being targeted. One of the most popular solutions to this problem has been the use of domain-specific languages (DSLs), which have been developed in several domains. this paper presents a new DSL for the data analytics domain, focusing FPGA execution. A human activity recognition (HAR) case study is used to both motivate the development of the DSL and evaluate it. Our results show that HAR systems can be targeted to an FPGA using the developed DSL. © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： field programmable gate arrays (FPGA)

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Runtime Verification on FPGAs with LTLf Specifications 20

Runtime Verification on FPGAs with LTLf Specifications

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20th international conference on Formal Methods in Computer-Aided Design, FMCAD 2020

作者： Tracy, Tommy Tabajara, Lucas M. Vardi, Moshe Skadron, Kevin University of Virginia CharlottesvilleVA22904 United States Rice University HoustonTX77005 United States

ISBN: (纸本)9783854480426

Runtime verification is a technique that evaluates a system's execution trace at runtime against a formal specification. this approach is particularly useful for safety-critical and autonomous systems to verify system functionality and allow for graceful recovery or intervention in the case of system faults. Specifications are often provided in a high-level form using some type of temporal logic, which can then be compiled into an automaton to be used as a monitor for the system. Existing work has mainly focused on implementing such monitors in software. In recent years there has been extensive research, however, in hardware acceleration of automata applications, which can potentially be extended to runtime monitoring. In this paper, we introduce an open-source framework for translating formulas in Linear Temporal logic over finite traces (LTLf) into automata implementations on FPGAs for high-efficiency and high-performance runtime monitoring. By using the spatial dimension of FPGAs, we run many of these automata in parallel, significantly reducing the latency between violation and monitor report and achieving significant throughput. We compare the performance of four different architectures corresponding to the combinations of deterministic or nondeterministic automata with an explicit or symbolic representation, and determine the design parameters that result in efficient hardware utilization and higher clock frequencies. We found that explicit automata tend to use more hardware resources, in particular Lookup Tables (LUTs), than symbolic automata. An exception to this is in the case of Flip-Flop (FF) usage, where symbolic DFAs tend to use more FF resources than explicit NFAs for smaller designs. We also found that explicit NFAs can run at higher clock frequencies, except for very large automata with high edge densities. Symbolic NFAs use fewer Look-Up Table resources and run at higher clock frequencies than symbolic DFAs, whereas symbolic DFAs required fewer Flip

关键词： field programmable gate arrays (FPGA)

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Accelerating design convergence of automata processing designs with a tiled hierarchy 6

Accelerating design convergence of automata processing desig...

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6th international Workshop on FPGAs for Software Programmers, FSP 2019, co-located with international conference on field programmable logic and applications, FPL 2019

作者： Tracy, Tommy Wadden, Jack Xie, Ted Skadron, Kevin Stan, Mircea University of Virginia CharlottesvilleVA United States University of Michigan Ann HarborMI United States University of Virginia CharlottesvilleVA United States Google Mountain ViewCA United States

ISBN: (纸本)9783800750467

Automata Processing is a parallel processing technique used to compute massive pattern matching queries on an input stream of data;among other applications, it is a popular approach to computing regular expressions. Automata processing with FPGAs achieves high performance by spatially representing these automata and distributing the input stream across all state machines to run in parallel. Existing automata-to-FPGA tools emit one, large, flat design lacking any hierarchy, where all automata sub-components make up one flat RTL file. We found that FPGA toolchains are poorly designed for large, flat designs and result in high synthesis times and poor Quality of Results. this limits the practical usefulness of current automata-on-FPGA approaches. We propose a technique to improve automata-to-FPGA mapping by automatically imposing a design hierarchy without changing RTL functionality, preventing the over-optimization in synthesis that led to excessively long compiler runtimes. We experimentally evaluate our technique by implementing an accelerated Learn to Rank machine learning automata application on FPGAs in Amazon's F1 cloud. We demonstrate successful place-and-route at full frequency of previously unsynthesizable designs and greatly reduced synthesis time (up to 50%) at a cost of a few percentage points more logic resources. © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： field programmable gate arrays (FPGA)

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A case study in using OpenCL on FPGAs: Creating an open-source accelerator of the autodock molecular docking software 5

A case study in using OpenCL on FPGAs: Creating an open-sour...

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5th international Workshop on FPGAs for Software Programmers, FSP 2018, co-located with international conference on field programmable logic and applications, FPL 2018

作者： Solis-Vasquez, Leonardo Koch, Andreas Group Darmstadt Germany

ISBN: (纸本)9783800747238

In recent years, OpenCL has been increasingly adopted as it enables software programmers to harness the performance and power efficiency of FPGAs. Despite simplifying the FPGA programming challenge, achieving high performance and energy efficiency with OpenCL is still a difficult task. In order to further contribute to the advance of the OpenCL usage for FPGAs, we utilize a realistic application scenario as our case study: the AutoDock molecular docking software. While OpenCL has proven its effectiveness in accelerating molecular docking on GPUs, for FPGA-based AutoDock accelerators it struggles with difficult design patterns. Besides complex multiple-producers to single-consumer datapaths, these include time-intensive loops with variable runtimes. therefore, this work presents the design and optimization steps for implementing AutoDock in OpenCL targeting an Arria-10 FPGA, as well as a corresponding execution runtime and energy-efficiency evaluation. Applying these techniques improved the performance of the initial OpenCL implementation for FPGAs by three orders of magnitude, with the final version of the code now yielding speed-ups of up to ∼2.7x, and energy-efficiency gains of up to ∼1.8x over the original serial AutoDock version executing on a current-generation CPU∗. © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： field programmable gate arrays (FPGA)

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HyperLogLog Sketch Acceleration on FPGA

HyperLogLog Sketch Acceleration on FPGA

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international conference on field programmable logic and applications

作者： Amit Kulkarni Monica Chiosa thomas B. Preußer Kaan Kara David Sidler Gustavo Alonso Systems Group ETH Zürich Switzerland ETH Zurich Switzerland Microsoft Corporation Redmond WA USA

ISBN: (数字)9781728199023

ISBN: (纸本)9781728199030

Data sketches are a set of widely used approximated data summarizing techniques. their fundamental property is sub-linear memory complexity on the input cardinality, an important aspect when processing streams or data sets with a vast base domain such as URLs, IP addresses, user IDs, etc. Among the many data sketches available, HyperLogLog has become the reference for cardinality counting i.e., how many distinct data items there are in a data set. Although it does not count every data item but provides probabilistic guarantees on the result thereby reducing its memory footprint, and the result is often used to analyze data streams. In this paper, we explore how to implement HyperLogLog on an FPGA to benefit from the parallelism available and the ability to process data streams coming from high-speed networks. Our multi-pipelined high-cardinality HyperLogLog implementation delivers 1.8x higher throughput than the best-optimized multi-thread HyperLogLog running on a dual-socket Intel Xeon E5-2630 v3 system with a total of 16 cores and 32 hyper-threads.

关键词： field programmable gate arrays Estimation Data processing Hardware Acceleration throughput TCPIP

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Efficient Floating-Point HUB Adder For FPGA

Efficient Floating-Point HUB Adder For FPGA

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international conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech)

作者： Machupalli Lahari Sonali Agrawal Amrita School of Engineering Bengaluru Amrita Vishwa Vidyapeetham India

ISBN: (数字)9781728192871

ISBN: (纸本)9781728192888

the utilization of Floating Point (FP) numbers had increased due to the complications of recent Digital signal processing (DSP) applications. In field-programmable gate arrays, to execute digital signal applications, HUB formats are used. By using this floating-point HUB format, the logic of rounding can be eliminated. the HUB format lessens the resource utilization and increases the speed of floating-point units. At the same time, it is providing the equivalent accuracy when compared to the conventional formats. In this paper, a double path floating-point HUB adder with Spurious Power Suppression Technique (SPST) is proposed. this adder is coded in Verilog, simulated and synthesized using Xilinx ISE 14.2 and Virtex-6 FPGA, xc6vlx240 is used to implement it. the performance of proposed adder is analysed and compared with existing double path HUB adder. the proposed HUB adder with SPST is improved with respect to power and delay as compare to existing HUB adder.

关键词： Adders Computer architecture Delays field programmable gate arrays Power demand logic gates Latches

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A Seamless DFT/FFT Self-Adaptive Architecture for Embedded Radar applications

A Seamless DFT/FFT Self-Adaptive Architecture for Embedded R...

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international conference on field programmable logic and applications

作者： Julien Mazuet Michel Narozny Catherine Dezan Jean-Philippe Diguet Thales LAS-France Élancourt France Lab-STICC CNRS UBO / UBS Brest France

ISBN: (数字)9781728199023

ISBN: (纸本)9781728199030

Radar is one of the domains where adaptability is paramount. Depending on the current system state, the radar algorithms must be adapted. However, most systems include static hardware implementations on FPGA or ASIC to process the massive amount of data from multiple sensors in parallel. the classic approach is to configure hardware logic through registers to switch radar modes, requiring to hardwire all configurations. However, in embedded radar systems the hardware resources are very limited and this solution is not optimal. An innovative solution relies on the FPGA reconfigurable nature to use multiple configurations and limit resources overhead. In this paper, we present a dynamic partial reconfiguration (DPR) application for radar processing, which allows to switch between a classic discrete Fourier transform (DFT) sum and a fast Fourier transform (FFT) to enhance Doppler extraction. Our study explores the pros and cons of both methods. Based on these observations, we propose a decision method for enabling an efficient self-adaptive solution. Finally, we provide a case study with a reconfigurable radar implementation which uses the current system state to take full advantage of both Fourier transform methods.

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