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检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

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Proceedings - 2010 international conference on field programmable logic and applications, FPL 2010: Message from the conference chairs

Proceedings - 2010 International Conference on Field Program...

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Proceedings - 2010 international conference on field programmable logic and applications, FPL 2010 2010年 xv页

作者： Ferrandi, Fabrizio Santambrogio, Marco D. Nurmi, Jari Politecnico di Milano Italy Tampere University of Technology Finland

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Proceedings - 2010 international conference on field programmable logic and applications, FPL 2010: Message from the steering committee

Proceedings - 2010 International Conference on Field Program...

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Proceedings - 2010 international conference on field programmable logic and applications, FPL 2010 2010年 xvi页

作者： Lysaght, Patrick Luk, Wayne Cheung, Peter Y.K. Xilinx Inc. United States Imperial College London United Kingdom

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Secure Medical Image Transmission Using the RLCD Algorithm

Secure Medical Image Transmission Using the RLCD Algorithm

引用

Sentiment Analysis and Deep Learning (ICSADL), international conference on

作者： C Sheeba Joice S Hitha Shanthini K Harsha S Gopika Department of Electronics and Communication Engineering Saveetha Engineering College Chennai India

ISBN: (数字)9798331523923

ISBN: (纸本)9798331523930

As digital platforms increasingly manage sensitive medical information, securing the transmission of medical images is essential to maintain confidentiality and data integrity. this project introduces an efficient and secure cryptographic framework specifically designed for medical image encryption using Reversible logic Cryptography Design (RLCD). the approach incorporates Linear Feedback Shift Registers (LFSR) combined with XOR gates, enabling low-power and high-speed encryption and decryption to protect patient data without sacrificing performance. By integrating reversible logic gates, this system effectively reduces energy dissipation and prevents information loss, making it well-suited for applications where data accuracy is critical. Implemented in Verilog HDL and deployed on a field programmable Gate Array (FPGA), this design provides a robust solution to address the unique security demands in medical imaging.

关键词： Sentiment analysis programmable logic arrays logic gates Hardware Software Encryption Hardware design languages field programmable gate arrays Biomedical imaging Python

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Meta-Heuristic Optimization of Custom Heterogeneous Blocks Defined eFPGA Design

Meta-Heuristic Optimization of Custom Heterogeneous Blocks D...

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international conference on VLSI Design

作者： D V Bhargav G Pradyumna Madhav Rao IIIT Bangalore

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

Modern field-programmable Gate Arrays (FPGAs) are highly versatile, with reconfigurable logic functionality that allows designers to create custom designs. Unlike traditional fixed-function integrated circuits, FPGAs are reconfigured multiple times to perform different tasks, making them ideal for various applications. An Embedded FPGA (eFPGA) takes the concept of an FPGA and integrates it as an IP core within a larger System-on-Chip (SoC) or Application-Specific Integrated Circuit (ASIC). the proposed work employs Non-dominated Sorting Genetic Algorithm-II (NSGA-II) to evolve efficient and high-performing eFPGA architectures with reduced critical path delay and power defined by a sufficient number of Configurable logic Blocks (CLBs), custom Digital Signal Processors (DSPs) and Block RAM (BRAMs) for targetting workload under consideration. As a result, this work presents a well-balanced eFPGA architecture layout obtained for four workloads equipped with different numbers of heterogeneous and configurable logic blocks. the results showed a significant improvement of 44.62% in hardware parameters.

关键词： Layout Metaheuristics Digital signal processors Signal processing algorithms Computer architecture Silicon Fabrics logic IP networks field programmable gate arrays

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Obstacle Avoidance: Transfer Learning and FPGA for Acceleration

Obstacle Avoidance: Transfer Learning and FPGA for Accelerat...

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Mobile Computing and Sustainable Informatics (ICMCSI), international conference on

作者： Jeyalakshmi. V Arjun Chakkrapani Preethaa Jansirani Kripa. S Vaithiyanathan. D Department of Electronics and Communication Engineering College of Engineering Guindy Chennai Tamil Nadu India Department of Electronics and Communication Engineering NIT Delhi India

ISBN: (数字)9798331522667

ISBN: (纸本)9798331522674

Obstacle detection and avoidance have historically been manual processes. With the advent of neural networks, many processing tasks have been made autonomous with more efficient by obtaining a wide variety of data from their surroundings to perform the next move. Training these networks is computationally intensive, which became the driving force behind transfer learning. field programmable Gate Arrays (FPGAs) which revolutionized reconfigurable logic is the next choice considered the opportunity to interleave the processing tasks between a general-purpose processor and dedicated logic blocks. Extending this concept to collision detection and using hardware acceleration to speed up the decision process can be highly beneficial, especially in such time critical applications. In this article, the idea above has been reviewed, and a method to implement the system has been proposed.

关键词： Training Neural networks Transfer learning Speech recognition Reconfigurable logic logic gates throughput Collision avoidance field programmable gate arrays Python

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Leveraging Dual Output LUTs with Pipelining for Efficient BCD to Binary Converter on FPGA

Leveraging Dual Output LUTs with Pipelining for Efficient BC...

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international conference on VLSI Design

作者： Santosh Kumar Ayan Palchaudhuri Department of Electronics & Communication Engineering School of Electrical and Computer Sciences Indian Institute of Technology Bhubaneswar Argul Khordha Odisha India

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

Decimal operands expressed in BCD is often the convenient data format used in embedded systems and human-centric applications. For optimized arithmetic computation on hardware where binary arithmetic can be conveniently processed, input BCD operands should first be converted to binary. this paper explores the versatility of FPGA specific logic primitives, namely the dual output Look-Up Tables (LUTs) and carry chain for efficient realization of parallel and pipelined architectures to optimize throughput and resource utilization for BCD to binary conversion architectures. Primitive instantiation was adopted to ensure design optimization, which involved direct configuration of FPGA logic primitives. the utility ratio of the configured FPGA primitives was increased to extract the best performance. Experimental results demonstrate a good trade-off in speed and area for our proposed architectures when compared with existing designs. We have investigated multiple implementation variants for the addition tree, which serves as a crucial functional logic block in the converter design.

关键词： Embedded systems Computer architecture Very large scale integration throughput Table lookup logic field programmable gate arrays Adders Optimization Arithmetic

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Research on Configuration Data Generation Algorithm for HyperParser

Research on Configuration Data Generation Algorithm for Hype...

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Power Electronics, Computer applications (ICPECA), IEEE international conference on

作者： Peijun Ma Gongzhi Zhao Jiangyi Shi Cong Yao Weitao Pan Xidian University Xi'an China

ISBN: (数字)9798331533694

ISBN: (纸本)9798331533700

the evolution of technologies such as Big Data, Cloud Computing, and Artificial Intelligence is inextricably linked to the transmission of network data. programmable network devices that facilitate high-speed processing are becoming increasingly crucial. the significance of programmable parsers, as a constituent element of programmable network devices, is readily apparent. HyperParser has the advantages of low latency, high throughput, small area, low power consumption, and full programmability, but its configuration data generation algorithm is inefficient and has limited optimality. In this paper, the inefficiency in running speed is first optimized by subtree partitioning, and the preference for removing certain columns more conducive to approaching the global optimal solution is then analyzed from a probabilistic point of view. Using the big-union, edge network and enterprise network three kinds of parse graph test, the original algorithm in processing big-union in 10min failed to end the run, processing the rest of the two parse graphs consumed 0.1545s, 0.1513s, extracted the number of key bits 7 and 18; the algorithm proposed in this paper processing the three kinds of parse graphs consumed 3.679s, 0.019s and 0.019s, 3.679s, 0.019s and 0.027s, and the number of key bits extracted are 160, 7 and 17 respectively.

关键词： Cloud computing Power demand Computer applications Big Data throughput Probabilistic logic Power electronics Partitioning algorithms Low latency communication Optimization

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Low Power Multiplier Using NAND logic Cells

Low Power Multiplier Using NAND Logic Cells

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international conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech)

作者： A. K. tharun B. Chakradhar Reddy M. Vinodhini Department of Electronics and Communication Engineering Amrita School of Engineering Bengaluru Amrita Vishwa Vidyapeetham India

ISBN: (数字)9798331520762

ISBN: (纸本)9798331520779

Different models of multiplier that offer the least power consumption are designed as technology node changes. the motive of the designers is to work on the minimization of power with less penalty in speed and area. the main focus of the present development is on the low power multiplier design for the different applications. this paper proposes a method of an efficient Wallace Tree Multiplier which is power efficient and uses a 7:3 counter consisting of full adders implemented using the NAND logic cells. this proposed design is synthesized in the Cadence Genus tool which uses a 45 nm technology library cell in CMOS. the detailed comparison is performed between two multipliers in which one is designed using 2: 1 multiplexers and Exor gates that already exist and the other using NAND logic cells which is proposed for 4-bit operands. the proposed design of the multiplier which uses NAND logic cells shows that it takes less power and has less delay when it is compared to the multiplier which uses 2: 1 Multiplexers and Exor gates. this design gives a good performance for both FPGA and ASIC platforms.

关键词： Multiplexing Power demand logic gates Minimization Libraries Hardware Delays logic field programmable gate arrays Adders

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Design and Implementation of an Efficient Quantum Cost Optimized Adder Using Reversible logic Gates

Design and Implementation of an Efficient Quantum Cost Optim...

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international conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech)

作者： Shatavisha Dasgupta Sourav Pandey Debjit Roy Agnik Maity Antarik Sinha Mihir Lal Saha dept. of Electronics and Communication Engineering Institute of Engineering & Management Under Univeristy of Engineering & Management kolkata Kolkata India

ISBN: (数字)9798331520762

ISBN: (纸本)9798331520779

In modern Very-Large-Scale Integration (VLSI) technology, managing information loss is a critical challenge. Conventional logic gates, such as AND, OR, and NOT, are prone to data loss during operations, reducing their efficiency for sophisticated applications. Reversible logic gates, which have an equal number of inputs and outputs, offer a solution by preserving data integrity. this paper presents the design and FPGA implementation of an efficient and high-speed full adder circuit utilizing reversible logic gates, namely Feynman, Toffoli, and Peres gates. the design focuses on improving computational efficiency and thermal performance. An analysis of the circuit's quantum cost, garbage outputs, and ancillary inputs reveals its advantages over traditional designs. Proposed design has been realized using Verilog and Synthesize and simulations performed using Xilinx Vivado and Xilinx ISE tools, confirms the functionality and efficiency of the proposed full adder. FPGA implementation of the design has been done using NEXYS A7 (Artix 7 series). the results show that the circuit has a quantum cost of 10, with two garbage outputs and one ancillary input, underscoring its potential for use in low-power, high-performance computing systems and quantum computing applications.

关键词： Performance evaluation Costs Quantum computing Simulation logic gates Very large scale integration thermal management Hardware design languages Adders field programmable gate arrays

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A Design of Fault-Tolerant System for Safety-Critical Systems

A Design of Fault-Tolerant System for Safety-Critical System...

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international conference on Autonomous Robots and Agents, ICARA

作者： Kai Yoshizawa Nobuyuki Yamasaki Graduate School of Science and Technology Keio University Yokohama Japan

ISBN: (数字)9798331509231

ISBN: (纸本)9798331509248

In safety-critical systems where failures or faults can lead to accidents, especially in special and harsh environments like those encountered in spacecraft, it is well known that multiple levels of errors can significantly increase the likelihood of system failure. For instance, system-level errors may occur due to cable breaks caused by severe vibrations, while gate-level errors can arise from radiation effects on System-on-Chip (SoC) semiconductors. Furthermore, in such specialized environments, human repair is often not feasible, necessitating that the system continue to operate even when a fault occurs in a part of it. therefore, this research discusses the design, implementation, and evaluation of a redundant system that combines multi-level redundancy mechanisms to tolerate multiple errors and maintain operation. the implementation was carried out on the Space I/O Core (SIOC), a System-on-Chip equipped with processors and I/O for distributed real-time systems. Additionally, bitstreams were created from the implemented logic, and the performance of the fault-tolerant system was evaluated using an actual FPGA.

关键词： Vibrations Space vehicles Redundancy Fault tolerant systems Termination of employment Switches logic gates System-on-chip field programmable gate arrays Robots

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