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检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

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Implementation of network application layer parser for multiple TCP/IP flows in reconfigurable devices

Implementation of network application layer parser for multi...

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16th international conference on field programmable logic and applications

作者： Moscola, James Cho, Young H. Lockwood, John W. Washington Univ Dept Comp Sci & Engn St Louis MO 63130 USA

ISBN: (纸本)9781424403127

this paper presents an implementation of a high-performance network application layer parser in FPGAs. At the core of the architecture resides a pattern matcher and a parser. the pattern matcher scans for patterns in high-speed streaming TCP data streams. the parser core augments each pattern found with semantic information determined from the patterns location within the data stream. the packet payload parser can provide a higher level of understanding of a data stream for many network applications. Such applications include high performance XML parsers, content-based/aware routers, and others. Additionally, a TCP processor allows stateful packet payload parsing of up to 8 million simultaneous TCP flows. the payload parser has been implemented in a Xilinx Virtex E 2000 FPGA on the field-programmable Port Extender platform. the parsing module runs,at 200 MHz and parse raw data at 6.4 Gbps. the payload parser, integrated with the TCP processor, runs at 100 MHz for a throughput of 3.2 Gbps.

关键词： field programmable gate arrays (FPGA)

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FPGA Accelerated FPGA Placement 29

FPGA Accelerated FPGA Placement

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29th international conference on field-programmable logic and applications (FPL)

作者： Dhar, Shounak Singhal, Love Iyer, Mahesh A. Pan, David Z. Univ Texas Austin ECE Dept Austin TX 78712 USA Intel Corp San Jose CA USA

ISBN: (纸本)9781728148847

Placement is one of the runtime bottlenecks in an FPGA design implementation flow, in which global placement accounts for a major portion of the runtime. In this paper, we demonstrate FPGA acceleration of wirelength gradient computation, which is an important part of modern analytical placement tools. To the best of our knowledge, this is the first work on acceleration of analytical placement on FPGAs. Our implementation uses OpenCL and leverages the FPGA's ability to support deep pipelines. We achieve an average speedup of 3.03x for wirelength gradient computation only and 2x for the entire global placement flow over a 28-threaded CPU implementation. Our placement quality is comparable to previously published works. Additionally, we can finish global placement for a design with 1 million cells and 1 million nets in less than 1 minute.

关键词： field programmable gate arrays Pins Acceleration Adders Runtime Tools Measurement

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A Systematic Approach to Design and Optimise Streaming applications on FPGA Using High-Level Synthesis 27

A Systematic Approach to Design and Optimise Streaming Appli...

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27th international conference on field programmable logic and applications (FPL)

作者： Hosseinabady, Mohammad Nunez-Yanez, Jose Luis Univ Bristol Dept Elect & Elect Engn Bristol Avon England

ISBN: (纸本)9789090304281

this paper proposes a systematic approach to help designers to optimise a given streaming application for FPGAs using High-Level Synthesis (HLS). the proposed technique specifically addresses the two main issues in a streaming application that are determining the exact amount of loop unrolling in the HLS code to increase the throughput and finding the optimum buffers' size to prevent deadlocks. To evaluate the proposed techniques two applications from the machine learning optimisation area are studied in the paper. these applications are Hessian-vector product and Conjugate Gradient (CG). the experimental results show up to 38x speed-up in throughput compared to the original streaming implementations provided by knowledgeable engineers using the dataflow, loop pipelining and FIFO channel related pragmas provided by the HLS tool. In addition, these applications show up to 2.98 GB/sec usage of memory bandwidth which is 93.1% of the total memory bandwidth available on the system. the source codes of the designs are available at https://***/Hosseinabady/csdfg-hls.

关键词： throughput Tools Systematics Optimization Bandwidth System recovery

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Using Novel Configuration Techniques for Accelerated FPGA Aging 30

Using Novel Configuration Techniques for Accelerated FPGA Ag...

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30th international conference on field-programmable logic and applications (FPL)

作者： Gaskin, Tanner Cook, Hayden Stirk, Wesley Lucas, Robert Goeders, Jeffrey Hutchings, Brad Brigham Young Univ Dept Elect & Comp Engn Provo UT 84602 USA

ISBN: (纸本)9781728199023

In this work we demonstrate a novel method of accelerating FPGA aging by configuring the FPGA to implement thousands of short circuits, resulting in high on-chip currents and temperatures. three ring oscillators are placed across the chip and are used to characterize the operating frequency of the FPGA fabric. Over the course of several weeks of running the short circuits, with daily characterization of the FPGA performance, we measured a decrease in FPGA frequency greater than 5%. After aging, the FPGA part was repeatedly characterized during a two week idle period. Results indicated that the slowdown did not change, and the aging appeared to be permanent. In addition, we demonstrated that this aging could be induced in a non-uniform manner. In our experiments, the short circuits were all placed in the lower two-thirds of the chip, and one of the characterization ring oscillators was placed at the top of the chip, outside of the region with the short circuits. the fabric at this location exhibited a 1.36% slowdown, only one-quarter the slowdown measured in the targeted region.

关键词： field programmable gate arrays (FPGA)

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Demonstration of a Multimode SoC FPGA-based Acoustic Camera 29

Demonstration of a Multimode SoC FPGA-based Acoustic Camera

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29th international conference on field-programmable logic and applications (FPL)

作者： da Silva, Bruno Segers, Laurent Braeken, An Touhafi, Abdellah VUB Dept Ind Sci INDI Brussels Belgium VUB Dept Elect & Informat ETRO Brussels Belgium

ISBN: (纸本)9781728148847

the relatively low-cost of the Micro-Electromechanical Systems (MEMS) microphones together with recent advances in the MEMS technology facilitates the construction of large MEMS microphone arrays, which are used to collect the acoustic information from certain beamed directions by applying beamforming techniques. the use of beamforming techniques to steer the microphone array response is the principle used by acoustic cameras to graphically display the acoustic information in a heatmap form. Our demonstrator exploits the heterogeneous nature of System-on-Chip (SoC) FPGA systems by generating real-time acoustic images on the FPGA component while alleviating the Wireless Sensor Networks (WSN) bandwidth limitations by performing acoustic image processing locally on the hard-core processor. As a result, a real-time acoustic heatmap is generated, enabling the visualization of the sound sources characteristics.

关键词： Acoustics Wireless sensor networks Cameras Micromechanical devices field programmable gate arrays Microphone arrays

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High throughput AES Encryption/Decryption with Efficient Reordering and Merging Techniques 27

High Throughput AES Encryption/Decryption with Efficient Reo...

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27th international conference on field programmable logic and applications (FPL)

作者： Li, Lijuan Li, Shuguo Tsinghua Univ Inst Microelect Beijing Peoples R China

ISBN: (纸本)9789090304281

this paper proposes a high throughput architecture for AES encryption/decryption targeting on the recent FPGAs with 6-input LUTs. Unlike previous works which share multiplicative inverse logics to realize SubBytes and InvSubBytes, the proposed architecture directly employs the look-up-table based Sbox for both SubBytes and InvSubBytes. Efficient reordering and merging techniques are applied to achieve a highly integrated encryption/decryption datapath with reduced area and delay. By sharing Sbox instead of inversion, the encryption datapath remains simple with unchanged MixColumns. For decryption, the linear operations including two inverse Affine functions and InvMixColumns between SubBytes are merged into a new InvMixColumns (NIMC-I) transformation. the NIMC-I is further optimized to reduce resources and share logics with MixColumns. through loop-unrolling and fair pipelining, the proposed 3-stage subpipelined design achieves 68.82 Gbps on XC7VX330T using 3930 slices and the 5-stage deep-pipelined one achieves 76.19 Gbps on XC6VLX240T using 4426 slices, which outperform previous equivalent designs in terms of throughput per area.

关键词： Encryption field programmable gate arrays throughput Merging Table lookup Pipeline processing

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FPGA-based Design of a Self-checking TMR Voter 27

FPGA-based Design of a Self-checking TMR Voter

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27th international conference on field programmable logic and applications (FPL)

作者： Afzaal, Umar Lee, Jeong A. Chosun Univ Dept Comp Engn Gwangju South Korea

ISBN: (纸本)9789090304281

the most common error mitigation scheme used for hardening designs against radiation-induced upsets on FPGAs is Triple Modular Redundancy (TMR). In a TMR system, there are three copies of a module and voting circuits that mask errors by voting for the majority. there are several types of voting circuits which can be classified based on their insertion sites in the design, functionality or the type of data structure to be mitigated. these voters are mostly built from Look-up Tables (LUTs) but these voters just like the design that is hardened by applying TMR are also susceptible to radiation-induced effects. In this paper, we present the design of a self-checking LUT based 1-bit voter intended for those sites where a TMR system reduces to a duplex or a simplex system. Voters on these sites make a single point of failure and the proposed design avoids this situation by attaching multiple voter redundancies to the same output. the operation of the proposed voter has been verified through its hardware implementation and timing simulation.

关键词： Tunneling magnetoresistance Table lookup field programmable gate arrays Switches Redundancy Integrated circuit reliability

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Detecting SEU-caused routing errors in SRAM-based FPGAs

Detecting SEU-caused routing errors in SRAM-based FPGAs

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18th international conference on VLSI Design/4th international conference on Embedded Systems Design

作者： Reddy, ESS Chandrasekhar, V Sashikanth, M Kamakoti, V Vijaykrishnan, N Indian Inst Technol Dept Comp Sci & Engn Madras 600036 Tamil Nadu India

ISBN: (纸本)0769522645

this paper proposes a new CLB architecture for FPGAs and an associated testing technique that detects routing errors caused by SEUs in the SRAM configuration memory of the FPGA. the proposed testing technique detects all possible routing errors including bridging faults, and requires a single configuration of only the LUTs of the FPGA. Any routing error that affects the logic of the circuit is detected by the proposed technique in a maximum of 8 clock cycles. It Is noteworthy that the time required for error detection is independent of both the number of switch matrices and the number of logic blocks in the FPGA.

关键词： field programmable gate arrays complex logic blocks single event upset routing errors fault tolerance graph theory vertex Coloring problem

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A Deep Learning Framework to Predict Routability for FPGA Circuit Placement 29

A Deep Learning Framework to Predict Routability for FPGA Ci...

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29th international conference on field-programmable logic and applications (FPL)

作者： Alhyari, A. Shamli, A. Abuwaimer, Z. Areibi, S. Grewal, G. Univ Guelph Sch Engn Guelph ON Canada Univ Guelph Sch Comp Sci Guelph ON Canada

ISBN: (纸本)9781728148847

the ability to accurately and efficiently estimate the routability of a circuit based on its placement is one of the most challenging and difficult tasks in the field programmable Gate Array (FPGA) flow. In this paper, we present a novel, deep-learning framework based on a Convolutional Neural Network model for predicting the routability of a placement. We also incorporate the deep-learning model into a state-of-the-art placement tool, and show how the model can be used to (1) avoid costly, but futile, place-and-route iterations, and (2) improve the placer's ability to produce routable placements for hard-to-route circuits using feedback based on routability estimates generated by the proposed model. the model is trained and evaluated using over 26K placement images derived from 372 benchmarks supplied by Xilinx Inc. Experimental results show that the proposed framework achieves a routability prediction accuracy of 97%, while exhibiting runtimes of only a few milliseconds.

关键词： Routing Integrated circuit modeling field programmable gate arrays Benchmark testing Heating systems Machine learning Predictive models

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Case for Fast FPGA Compilation using Partial Reconfiguration 28

Case for Fast FPGA Compilation using Partial Reconfiguration

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28th international conference on field programmable logic and applications (FPL)

作者： Park, Dongjoon Xiao, Yuanlong Magnezi, Nevo DeHon, Andre Univ Penn Dept Elect & Syst Engn Philadelphia PA 19104 USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Despite the FPGA's advantages over other hardware platforms, long compilation time prevents FPGA engineers from efficiently exploring the design space and discourages new users who want to quickly iterate for debugging. To reduce compilation time, this work adopts a divide-and-conquer approach using Partial Reconfiguration with a Packet-Switched Fat-Tree network. Partially reconfigured leaves in the packet-switched network are independent from each other and can be compiled separately in parallel. Also, when a minor fix is required to a bitstream, only the corresponding leaves need to be incrementally compiled. Preliminary experimental evidence from our work-in-progress effort illustrates how a 30 minute full-chip compile time can be reduced to 7 minutes.

关键词： field programmable gate arrays Table lookup Overlay networks Runtime Tools Hardware Standards

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