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检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

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FPGA-Driven DAC with Second Order Sliding Mode Control of Filter Model for Hardware-In-the-Loop Simulators 18

FPGA-Driven DAC with Second Order Sliding Mode Control of Fi...

引用

18th IEEE international Power Electronics and Motion Control conference (IEEE PEMC)

作者： Kokenyesi, Tamas Hegedus, Marton Vereb, Szabolcs Balogh, Attila Suto, Zoltan Varjasi, Istvan Budapest Univ Technol & Econ Dept Automat & Appl Informat H-1117 Budapest Hungary

ISBN: (纸本)9781538641989

the advances in FPGA technology have enabled to develop fast HIL (Hardware-in-the-Loop) simulators, revolutionizing control software and hardware development for power electronics. HIL simulators should reproduce the same analogue signals that could be measured on real main circuits. A very common limitation in these applications is the usable pin count of the FPGA, therefore using the most pin-effective Digital-to-Analogue Converters (DACs) becomes critical. Sigma - Delta DACs provide a simple, FPGA-synthesizable solution using a single pin for each output, but the output signal's bandwidth and latency is usually not sufficient, because of the required analogue filters. Higher order Sigma - Delta DACs usually perform much better in the aspect of the Signal-to-Noise-Ratio (SNR) but not the usable bandwidth. this paper introduces a new bitstream DAC architecture based on the sliding mode control of the output analogue filter model. It is optimized mainly to reproduce current transducer signals in power electronics (usually triangle waves), which can be done more accurately than traditional Sigma - Delta solutions.

关键词： field programmable gate arrays Pins Sliding mode control Signal to noise ratio Bandwidth Modulation Voltage control

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the FPGA-Based Problem-Oriented On-Board Processor

The FPGA-Based Problem-Oriented On-Board Processor

引用

IEEE international conference on Intelligent Data Acquisition and Advanced Computing Systems

作者： Volodymyr Opanasenko Alexander Palahin Stanislav Zavyalov V.M. Glushkov Institute of Cybernetics of NAS of Ukraine Kyiv Ukraine Radionix Limited Company Kyiv Ukraine

the FPGA-based problem-oriented processor for the implementation of robust algorithms for estimating the state vector and for the control of the small spacecraft is developed. Comparison and analysis of calculation results of new ellipsoid center obtained for the C-program model as well as the developed core of problem-oriented processor for the estimation of ellipsoidal state and for control algorithms are performed.

关键词： Ellipsoids field programmable gate arrays Estimation Uncertainty Space vehicles Control systems Robustness

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SMEM++: A pipelined and time-multiplexed SMEM seeding accelerator for genome sequencing 28

SMEM++: A pipelined and time-multiplexed SMEM seeding accele...

引用

28th international conference on field-programmable logic and applications, FPL 2018

作者： Cong, Jason Guo, Licheng Huang, Po-Tsang Wei, Peng Yu, Tianhe University of California Los Angeles United States National Chiao Tung University Taiwan

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

Next-generation sequencing motivates the researchof FPGA acceleration for genome sequencing algorithms. therecently developed quadratic-time SMEM seeding algorithmbecomes a time-consuming computation kernel in genomesequencing, but it has not been well studied. the fundamentalchallenge of accelerating the SMEM algorithm is to handle itslarge volume of random memory accesses. While the state-ofthe-art SMEM accelerator attempts sacrifices the performanceof individual processing elements to maximize the task-levelparallelism, this methodology suffers a serious resource underutilizationissue. therefore, we propose SMEM++, a pipelinedand time-multiplexed FPGA accelerator for SMEM ***++ adopts the canonical non-blocking pipelinemethodology and implements a fully pipelined acceleratorwith initiation interval equal to one. Moreover, we designa communication interface adapter to make the acceleratorcompatible to the target platform interface and increase itsportability. Experiments on the Intel HARPv2 platform showthat SMEM++ outperforms the original software by 24x, andoutperforms the state-of-the-art SMEM accelerator design by6.3x, with 43% less logic resource usage. © 2018 IEEE.

关键词： field programmable gate arrays (FPGA)

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Glitch Recall: A Hardware Trojan Exploiting Natural Glitches in logic Circuits 18th

Glitch Recall: A Hardware Trojan Exploiting Natural Glitches...

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18th World international conference on Information Security and Application (WISA)

作者： Joh, Jungwoo Seo, Yezee Kim, Hoon-Kyu Kwon, Taekyoung Yonsei Univ Informat Secur Lab Seoul 03722 South Korea Agcy Def Dev Seoul South Korea

ISBN: (纸本)9783319935638;9783319935621

As the IoT era comes to the full-fledged, hardware Trojans that involve malicious modifications of circuitry are becoming a growing security concern. To avoid a detection mechanism, hardware Trojans may need a stealthy nature in their existence for being dormant, and even when triggered. In this paper, we devise a new hardware Trojan concept that exploits natural glitches and their control mechanisms for information leakage in a stealthy manner. We indeed reversely exploit the glitch control mechanisms to be bypassed when triggered, and try to recall the natural glitches for the purpose. An adversary who triggered the hardware Trojan may infer multiple input values from a single output of the target logic, thereby obtaining multiple outputs of the preceding logics, by monitoring the existence of the natural glitches. We perform experiments and discuss the results and threats, not to be neglected, along with a possible mitigation.

关键词： Hardware Trojan Glitch Hazard Glitch control Multiplexer programmable delay element

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CAD Tool Flow for Variation-Tolerant Non-Volatile STT-MRAM LUT based FPGA 2018

CAD Tool Flow for Variation-Tolerant Non-Volatile STT-MRAM L...

引用

7th international conference on Software and Computer applications (ICSCA)

作者： Kim, Jeongbin Kim, Ki Tae Chung, Eui-Young Yonsei Univ Dept Elect & Elect Engn Seoul South Korea

ISBN: (纸本)9781450354141

field programmable Gate Array (FPGA) is a reconfigurable circuit and it is used for various applications such as image processing, digital signal processing and neural network. FPGA adopts a logic circuit called Look-Up Table (LUT) as a basic circuit structure. Commonly used FPGAs have volatile characteristic because it consists of SRAM based LUT that adopts SRAM as a memory cell. Volatile FPGAs have a disadvantage in terms of power management efficiency. Variation-Tolerant Non-Volatile STT-MRAM (VTNV) LUT has been studied for a nonvolatile FPGAs and it has unique characteristics that can only operate in the half clock period. Accordingly, VTNV LUT based FPGA cannot operate normally with conventional FPGA CAD tool flow. We propose FPGA CAD (Computer Aided Design) tool flow for VTNV LUT based FPGA with supporting unique characteristic of VTNV LUT, and implement a non-volatile FPGA. through proposed FPGA CAD tool flow, non-volatile FPGA based on VTNV LUT could operate normally. Because of high parameters of VTNV LUT, experimental results show that power increases by 29% and critical path delay increases by 16%, but it'll be improved sufficiently by future VTNV LUT researches.

关键词： Computer aided design (CAD) field programmable gate array (FPGA) CAD tool flow non-volatile FPGA

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Representation of Markov Functions by Minimal Polynomials over a Finite field 4

Representation of Markov Functions by Minimal Polynomials ov...

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4th international conference on Information Technology and Nanotechnology, ITNT 2018

作者： Zakharov, V.M. Shalagin, S.V. Eminov, B.F. KNRTU-KAI Karl-Marx str. 10 Kazan420111 Russia

the method of representing Markov functions with minimal characteristic polynomials over a finite field is proposed. these polynomials are defined on the basis of integrated stochastic matrices. the representation accuracy of stochastic matrices is linearly dependent on the minimum degree of the polynomials. the algorithmic implementation of the method is shown to build a sequence of the Markov functions class considered, with a given linear complexity. © 2018 Institute of Physics Publishing. All rights reserved.

关键词： Polynomials

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Data Piecewise Linear Approximation for Bearings Degradation Monitoring

Data Piecewise Linear Approximation for Bearings Degradation...

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IEEE international conference on Intelligent Data Acquisition and Advanced Computing Systems

作者： Fei Huang Alexandre Sava Kondo H. Adjallah Zhouhang Wang Huaiyin Institute of Technology Huaian Jiangsu P.R. China Université de Lorraine Metz FRANCE

In this paper, we propose a method based on piecewise linear approximation (PLA) with segmented projection error (SPE) to reveal the underlying correlation structures and approximate multivariate time series. Based on this method we elaborate an indicator called vector of segmented projection error (VSPE) to characterize the bearings degradation using standard time domain standard features extracted from the vibration signal. the indicator VSPE monitors the evolution of the entire degradation process efficiently and provides real-time information on bearings degradation. We show the effectiveness of this new indicator using benchmark data. the results reveal the sensitive and monotonic character of the indicator VSPE according to the bearings degradation, which is promising for monitoring bearings on their lifespan.

关键词： Degradation Time series analysis Feature extraction Standards Vibrations Monitoring programmable logic arrays

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AutoRARE: An Automated Tool For Generating FPGA-Based Multi-Memory Hardware Accelerators For Compute-Intensive applications 37

AutoRARE: An Automated Tool For Generating FPGA-Based Multi-...

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37th IEEE international Performance Computing and Communications conference (IPCCC)

作者： Jadhav, Shrikant S. Gloster, Clay Doss, Christopher Kim, Youngsoo Naher, Jannatun North Carolina A&T State Univ Dept Elect & Comp Engn Greensboro NC 27401 USA North Carolina A&T State Univ Dept Comp Syst Technol Greensboro NC USA Bradley Univ Dept Elect & Comp Engn Peoria IL 61625 USA

ISBN: (纸本)9781538668085

In this paper, we present AutoRARE, a Java-based automated design tool for generating field programmable Gate Array (FPGA)-based hardware accelerators. AutoRARE automatically generates all VHDL models needed to build/synthesize a processor specifically tailored for each application. the user needs only provide the VHDL description of a special-purpose floating point Arithmetic logic Unit (ALU) or function core. the tool generates the VHDL description for the memory interface, memory controller, host processor interface, and the application specific processor. We also present details of the FPGA-based multi-memory hardware accelerator for accelerating computationally intensive applications, generated using AutoRARE. the multi-memory hardware accelerator is highly pipelined and able to simultaneously read and write multiple floating point values from multiple memories. the multi-memory architecture is the key to providing hardware accelerators that execute 10X-100X faster than typical multi-core processors. the Taylor Series expansion of the sine/cosine function is used as an application to demonstrate the merits of the multi-memory hardware accelerator. In our experiments, we executed the Taylor Series in software and compared execution times with an FPGA-based hardware implementation. Our experiments show that the FPGA-based multi-memory Taylor Series hardware accelerator is 481X faster than software executing the Taylor Series on a typical server.

关键词： Reconfigurable Computing field-programmable Gate Arrays field-programmable Custom Computing Machines High Performance Computing Multi-Memory Architecture Multiple Memory Banks

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MLP on FPGA: Optimal Coding of Data and Activation Function

MLP on FPGA: Optimal Coding of Data and Activation Function

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IEEE international conference on Intelligent Data Acquisition and Advanced Computing Systems

作者： Farid Alilat Reda Yahiaoui Laboratory of Image Processing and Radiation Algiers Algeria

An efficient coding leading to the implementation on FPGA of an optimal architecture of a multilayer Perceptron is proposed. the implementation of this architecture meets the requirements of embark, on the one hand by minimizing the consumed power, the execution time, the logical resources used, etc ..) and on the other hand by ensuring the portability of the computer application (the ability of the latter to run on different platforms and environments). Massive parallelization, efficient coding of the sigmoid and pipeline processing are used. the neuronal approach developed and implemented on FPGA was evaluated in the context of the application on objective criteria according to the two aspects of software and hardware. the results obtained are in line with expectations and objectives.

关键词： Neurons field programmable gate arrays Encoding Random access memory Computer architecture Clocks Hardware

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Modular Signal Processing Unit for Motion Control applications Based on System-on-Chip with FPGA

Modular Signal Processing Unit for Motion Control Applicatio...

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international conference on Emerging Technologies and Factory Automation (ETFA)

作者： Vlastimil Šetka Ondřej Ježek Rihards Novickis NTIS – New Technologies for the Information Society Research Center University of West Bohemia Pilsen Czech Republic EDI – Institute of Electronics and Computer Science Riga Latvia

Motion control systems with distributed architecture where multiple input/output devices are connected to the upper layer controller by fast digital communication (fieldbus) became an industrial standard. this paper presents design of a modular input/output device which can process signals from multiple sensors, drive multiple actuators and act as a Slave or Master node in EtherCAT fieldbus network. User-defined algorithms can be easily implemented to preprocess input signals, combine multiple signals or close local control loops with extremely high sampling rates which makes the difference to standard off-the-shelf solutions. To meet these requirements and simplify hardware design, our device is based on System-on-Chip with both programmable logic (FPGA) and classic processor (CPU) ARM cores. Data processing including user algorithms can be done entirely in FPGA which provides very low latency and no jitter, and also on CPU for more complex computations with advantage of tight integration between FPGA and CPU. In this paper we provide description of hardware design, system architecture and typical applications.

关键词： field programmable gate arrays Universal Serial Bus Central Processing Unit Hardware Ethernet Random access memory

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