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A hardware/software co-design approach for real-time binocular stereo vision based on ZYNQ (Short Paper) 14th

A hardware/software co-design approach for real-time binocul...

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14th EAI international conference on Collaborative Computing: Networking, applications and Worksharing, CollaborateCom 2018

作者： Pan, Yukun Zhu, Minghua Luo, Jufeng Qiu, Yunzhou Hardware/Software Co-Design Technology and Application Engineering Research Center East China Normal University Shanghai200062 China Shanghai Internet of Things CO. LTD Shanghai201899 China

ISBN: (纸本)9783030129804

Based on the ZYNQ platform, this paper proposes a hardware/software co-design approach, and implements a binocular stereo vision system with high real-time performance and good human-computer interaction, which can be used to assist advanced driver assistance systems to improve driving safety. Combining the application characteristics of binocular stereo vision, the approach firstly modularizes the system’s functions to perform hardware/software partitioning, accelerates the data processing on FPGA, and performs the data control on ARM cores;then uses the ARM instruction set to configure the registers within FPGA to design relevant interfaces to complete the data interaction between hardware and software;finally, combines the implementation of specific algorithms and logical control to complete the binocular stereo vision system. the test results show that the frame rate with an image resolution of 640 * 480 can reach 121.43 frames per second when the FPGA frequency is 100M, and the frame rate is also high for large resolution images. At the same time, the system can achieve real-time display and human-computer interaction with the control of the graphical user interface. © 2019, ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering.

关键词： field programmable gate arrays (FPGA)

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Implementation of high-performance floating point divider using pipeline architecture on FPGA 1

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6th international conference on Frontiers of Intelligent Computing: theory and applications, FICTA-2017

作者： Hanuman, C.R.S. Kamala, J. Department of Electronics and Communication Engineering College of Engineering Guindy Anna University Chennai India

ISBN: (数字)9789811075667

ISBN: (纸本)9789811075650

Data intensive DSP algorithms mostly depend on double precision (DP) floating point arithmetic operations. With advanced FPGA devices, applications need more floating point arithmetic operations to accelerate reconfigurable logic. Important and complex applications heavily depend on the floating point divider (FPD) blocks. this paper illustrates implementation of low-latency dividers based on pipelining, which is operated at 30% faster than existing divider. DPFPD implemented using field programmable gate array (FPGA) outperforms other ULP dividers. Pipelining architecture of FPD increases the throughput and reduces the power considerably. the architecture is validated for standalone as well as integrated application levels. © Springer Nature Singapore Pte Ltd. 2018.

关键词： field programmable gate arrays (FPGA)

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the Basic Model of Attack Resistance Estimation for Monitoring the Program Code Integrity of the FPGA-Based Systems

The Basic Model of Attack Resistance Estimation for Monitori...

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IEEE international conference on Intelligent Data Acquisition and Advanced Computing Systems

作者： Kostiantyn Zashcholkin Oleksandr Drozd Oleg Sachenko Olena Ivanova Yurii Boliubash Odessa National Polytechnic University Odessa Ukraine Ternopil National Economic University Ternopil Ukraine Zolochiv College National University Lviv Polytechnic Zolochiv Ukraine

An approach to monitoring the program code integrity of FPGA-based systems is considered. the approach is based on the use of a digital watermark to store monitoring information. As part of this approach, an integrity monitoring method is considered, which is characterized by the use of several rounds of the embedding of a digital watermark in a program code. A basic model for estimation the complexity of the attack on the integrity monitoring method is proposed. the model takes into account the possible directions of attack, both related to the storage of monitoring information in the form of a digital watermark, and the direction of attack due to the traditional mechanisms for protection of the method. With the help of the proposed model, the stages of the attack, which appear during the transition from traditional methods of storing control information to its storage in the form of a digital watermark, are shown.

关键词： Monitoring Watermarking Estimation field programmable gate arrays Complexity theory Computational modeling Cryptography

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Energy-efficient hardware caching decision using Fuzzy logic in Mobile Edge Computing 6

Energy-efficient hardware caching decision using Fuzzy Logic...

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6th IEEE Int Conf on Future Internet of things and Cloud (W-FiCloud) / 15th Int Conf on Mobile Web and Intelligent Information Systems (MobiWis) / 4th Int Conf on Big Data Innovations and applications (Innovate-Data)

作者： Mehamel, Sarra Slimani, Khaled Bouzefrane, Samia Daoui, Mehammed Univ Mouloud Mammeri LARI Lab Tizi Ouzou Algeria Conservatoire Natl Arts & Metiers CEDRIC Lab Paris France

ISBN: (纸本)9781538678107

To bring data contents and services in close proximity to the mobile user, mobile edge networks are good candidate because they provide cloud computing and caching capabilities at the edge of cellular networks, hence offering proximity that ensures low latency and high bandwidth through the concept of Mobile Edge Computing (MEC) [22]. To supply effective caching services in the highly resource-constrained and dynamically mobile environment, we propose an energy-efficient fuzzy caching technique for edge devices. this technique uses various parameters (such as mobility and requests frequency) to ensure the effectiveness of our proposed mechanism that highlights the challenge of the computational complexity in mobile edge computing. In this paper, our contribution is a novel solution based on a hardware implementation that uses field-programmable Gate Array (FPGA) as an alternative computational architecture that cuts overall energy requirements. Preliminary implementation and evaluation results demonstrate that the proposed solution reduces the energy consumption and the server load of the edge devices by using an FPGA implementation for fuzzy logic caching decision.

关键词： Edge caching mobile edge computing fuzzy logic energy FPGA

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FPGA Implementation of Internet Key Exchange Based on Chaotic Cryptosystem

FPGA Implementation of Internet Key Exchange Based on Chaoti...

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IEEE international conference on Intelligent Data Acquisition and Advanced Computing Systems

作者： Belqassim Bouteghrine Mohammed Rabiai Camel Tanougast Said Sadoudi LCOMS Universite de Lorraine Ecole Superieur Ali Chabati Laboratoire Telecommunications Ecole Militaire Polytechnique

ISBN: (纸本)9781728140704

In network communication domain, one of the most widely used protocol for encrypting data and securing communications is the IPSec protocol. the design of this protocol is based on two main phases which are: exchanging keys phase and transferring data phase. In this paper we focus on enhancing the exchanging keys phase which is included in the security association (SA), using a chaotic cryptosystem. Initially IPSec is based on the Internet Key Exchange (IKE) protocol for establishing the SA. Actually IKE protocol is in charge for negotiating the connection and for authenticating both nodes. However;using IKE gives rise to a major problem related to security attack such as the Man in the Middle Attack. In this paper, we propose a chaotic cryptosystem solution to generate SA file for the connected nodes of the network. By solving a 4-Dimension chaotic system, a SA file that includes 128-bit keys will be established. the proposed solution is implemented and tested using FPGA boards.

关键词： Network protocol IPSec SA IKE Chaotic cryptosystem FPGA Internet key exchange IPsec Network protocols field programmable gate arrays cryptography protocols connected node

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Spatial-Temporal Transformation of Matrix and Multilayer Algorithms of Binary Number Multiplication

Spatial-Temporal Transformation of Matrix and Multilayer Alg...

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IEEE international conference on Intelligent Data Acquisition and Advanced Computing Systems

作者： Volodymyr Gryga Igor Kogut Victor Holota Roman Kochan Stanislaw Rajba Tomasz Gancarczyk Uliana Iatsykovska Vasyl Stefanyk Precarpathian National University University of Bielsko-Biala

ISBN: (纸本)9781728140704

the paper conducted analysis of matrix and multilayer structures of algorithms for multiplication of binary numbers and determined their advantages and disadvantages. the hardware and time characteristics of matrix and multilayer binary number multipliers with the use of improved structures of single-digit full and half adders are investigated. Using theory of spatio-temporal graphs recursive multistep structures of the multipliers are developed. the analytical expressions for evaluation of the complexity of developed multiplier structures are obtained. It is determined that the algorithmic and conveyor structures of the multipliers have high speed and require significant hardware complexity, in contrast to the proposed multi-cycle structures that have significantly lower performance, but the hardware complexity and the corresponding occupied area on the crystal are minimal. Synthesis of developed multiplier structures on the Xilinx FPGA is performed and the convergence of theoretical and practical results of researches is shown.

关键词： Matrix and multilayer multiplier Algorithm Multistep multiplier Flow and spatiak-temporal graph FPGA Binary digits Multiplying circuits algorithms field programmable gate arrays matrices Computer hardware Multiplication matrix multilayer structures

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Power and Delay Optimization of FinFET based Adiabatic logic SRAM Cell

Power and Delay Optimization of FinFET based Adiabatic Logic...

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IEEE international conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)

作者： B Ganesh Kumar Shivakumar V Gaded P Srividya R V College of Engineering Bengaluru India

ISBN: (数字)9781728106304

ISBN: (纸本)9781728106311

the present-day scenario, the VLSI field has grown significantly and the restraints on the critical factors such as power, area & speed have tightened to greater extent. the requirement of high speed and low power applications and their efficiency is the need of the hour. the Static Random-Access Memory [SRAM] cell is the most commonly used memory cell for retaining the data until the power supply is active. In this paper we approach to optimize the power and delay constraints of the SRAM cell. the approach uses FinFET technology as well as the Adiabatic logic approach to meet the required constraints. FinFET based designs proves to be more efficient with faster switching speeds and better power delay product compared to conventional CMOS. the Adiabatic logic further helps in power reduction by using the stored energy. In this paper, the different types of adiabatic logics are applied to SRAM cell designed using 18nm FinFETs to reduce power consumption and delay. It is observed that Efficient Charge Recovery logic [ECRL] is most optimized in terms of power consumption and Body-Biasing technique is more efficient in terms of delay as it provides faster switching.

关键词： Adiabatic Delays SRAM cells FinFETs Power demand

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Real-time heterogeneous stream processing with NaNet in the NA62 experiment 18

Real-time heterogeneous stream processing with NaNet in the ...

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18th international Workshop on Advanced Computing and Analysis Techniques in Physics Research (ACAT)

作者： Ammendola, R. Barbanera, M. Biagioni, A. Cretaro, P. Frezza, O. Lamanna, G. Lo Cicero, F. Lonardo, A. Martinelli, M. Pastorelli, E. Paolucci, P. S. Piandani, R. Pontisso, L. Rossetti, D. Simula, F. Sozzi, M. Valente, P. Vicini, P. INFN Roma Ple A Moro 2 I-00185 Rome Italy INFN Roma Tor Vergata Via Ric Sci 1 I-00133 Rome Italy Pisa Univ Largo B Pontecorvo 3 I-56127 Pisa Italy INFN Pisa Largo B Pontecorvo 3 I-56127 Pisa Italy nVIDIA Corp 2701 San Tomas Expressway Santa Clara CA 95050 USA

the use of GPUs to implement general purpose computational tasks, known as GPGPU since fifteen years ago, has reached maturity. applications take advantage of the parallel architectures of these devices in many different domains. Over the last few years several works have demonstrated the effectiveness of the integration of GPU-based systems in the high level trigger of various HEP experiments. On the other hand, the use of GPUs in the DAQ and low level trigger systems, characterized by stringent real-time constraints, poses several challenges. In order to achieve such a goal we devised NaNet, a FPGA-based PCI-Express Network Interface Card design capable of direct ( zero-copy) data transferring with CPU and GPU ( GPUDirect) while online processing incoming and outgoing data streams. the board provides as well support for multiple link technologies ( 1/10/40GbE and custom ones). the validity of our approach has been tested in the context of the NA62 CERN experiment, harvesting the computing power of last generation NVIDIA Pascal GPUs and of the FPGA hosted by NaNet to build in real-time refined physics-related primitives for the RICH detector ( i.e. the Cerenkov rings parameters) that enable the building of more stringent conditions for data selection in the low level trigger.

关键词： field programmable gate arrays (FPGA)

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Multiple hash matching units (MHMU): An algorithmic ternary content addressable memory design for field programmable gate arrays 19

Multiple hash matching units (MHMU): An algorithmic ternary ...

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19th IEEE international conference on High Performance Switching and Routing, HPSR 2018

作者： Reviriego, Pedro Pontarelli, Salvatore Ullah, Anees Zahir, Ali Bianchi, Giuseppe ARIES Research Center Universidad Antonio de Nebrija Spain Italy Department of Electrical and Computer Engineering Center of Advanced Studies in Engineering Pakistan Department of Electrical Engineering COMSATs Institute of Information Technology Pakistan University of Rome Tor Vergata Italy

ISBN: (纸本)9781538678015

As applications and user requirements are constantly evolving, there is a need to provide flexible networks that are able to process packets at high speed. One of the basic functions used for packet processing is matching a key formed by some fields of the incoming packet header against a set of stored rules. this is done for example to determine the next hop of a packet or to apply security checks on a firewall. In many cases, the stored rules have do not care bits as that enables a more flexible and compact representation of the rules. therefore, the matching can be done in hardware using Ternary Content Addressable Memories (TCAMs). However, TCAMs pose several problems in many implementations. For example, for ASICs they require much more circuit area and power than standard SRAMs. On the other hand, designs based on programmable logic such as field programmable Gate Arrays (FPGAs) can only use the blocks provided by the FPGA that do not typically include TCAMs. In this last case, a TCAM can be emulated using the FPGA logic resources but with a large cost. To reduce the cost of implementing TCAMs, a number of algorithmic solutions have been proposed and are known as Algorithmic TCAMs or A-TCAMs. Most of those schemes target either software or ASIC implementations. In this paper we present Multiple Hash Matching Units (MHMU) an A-TCAM solution targeted towards FPGA implementations. the proposed scheme exploits the massive parallelism of FPGAs to implement many hash based matching units that use the embedded block RAM memories of the FPGA. the proposed MHMU scheme has been mapped to a Xilinx series 7 FPGA to check its efficiency in terms of resource usage and its scalability. To validate the effectiveness of MHMU, a simple configuration has been tested with Classbench generated sets of rules. the results show that the MHMU is able to consistently accommodate sets with several tens of thousands of rules with large keys. © 2018 IEEE.

关键词： Static random access storage

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Ultra Low-Power Encryption/Decryption Core for Lightweight IoT applications

Ultra Low-Power Encryption/Decryption Core for Lightweight I...

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international Computer Engineering conference (ICENCO)

作者： Ahmed Zaky Eslam Elmitwalli Mostafa Hemeda Yehea Ismail Khaled Salah University of Science and Technology at Zewail City October Gardens Egypt Center of Nanoelectronics and Devices (CND) American University in Cairo Zewail City of Science and Technology Mentor a Siemens Business Egypt

ISBN: (数字)9781728151465

ISBN: (纸本)9781728151472

the fact that security is not the main functionality of an IoT device means that even lesser portion of its computing power is available for security. Security measures implemented in traditional computers such as cryptography, present a challenge from this context when applied in IoT devices. Different algorithms have been presented in the literature that meet IoT requirements and yet maintain the needed security level. Most of the studies have focused on popular algorithms, especially AES finalists. However, more IoT oriented algorithms have been presented to provide better performance in terms of power and capacity, those are known as lightweight cryptographic algorithms. PRESENT as one of the lightweight cryptographic algorithms is the main focus of this study. the algorithm has been implemented using MATLAB, ASIC and FPGA flows. Lowest achievable power consumption is 120.9 μW at throughput of 20.64 Mbps for the ASIC. For the FPGA, best achievable results was for 16 s-box design utilizing a power of 225.95 mW and 352 LUTs.

关键词： field programmable gate arrays Clocks Power demand Cryptography Matlab logic gates

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