检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,875 篇 会议
28 篇 期刊文献
7 册 图书

馆藏范围

1,910 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,242 篇 工学
- 1,040 篇 计算机科学与技术...
- 729 篇 软件工程
- 406 篇 电气工程
- 183 篇 电子科学与技术（可...
- 74 篇 信息与通信工程
- 63 篇 控制科学与工程
- 36 篇 仪器科学与技术
- 30 篇 机械工程
- 26 篇 动力工程及工程热...
- 23 篇 建筑学
- 17 篇 土木工程
- 15 篇 核科学与技术
- 13 篇 光学工程
- 13 篇 生物工程
- 10 篇 材料科学与工程（可...
- 10 篇 生物医学工程（可授...
- 8 篇 安全科学与工程
170 篇 理学
- 101 篇 数学
- 45 篇 物理学
- 18 篇 生物学
- 16 篇 系统科学
- 9 篇 统计学（可授理学、...
- 6 篇 化学
49 篇 管理学
- 38 篇 管理科学与工程(可...
- 19 篇 工商管理
- 14 篇 图书情报与档案管...
16 篇 医学
- 14 篇 临床医学
- 12 篇 特种医学
14 篇 法学
- 12 篇 社会学
9 篇 经济学
- 9 篇 应用经济学
5 篇 农学
5 篇 军事学
2 篇 教育学

主题

832 篇 field programmab...
688 篇 field programmab...
276 篇 hardware
156 篇 computer archite...
125 篇 logic gates
112 篇 table lookup
87 篇 throughput
87 篇 clocks
83 篇 random access me...
79 篇 routing
74 篇 software
72 篇 acceleration
65 篇 delays
65 篇 optimization
62 篇 kernel
54 篇 registers
54 篇 logic
50 篇 switches
49 篇 algorithm design...
47 篇 system-on-chip

机构

14 篇 univ toronto dep...
9 篇 imperial coll lo...
8 篇 school of comput...
8 篇 department of co...
8 篇 ecole polytech f...
7 篇 univ british col...
7 篇 brigham young un...
7 篇 imperial coll lo...
7 篇 tokyo inst techn...
6 篇 univ tsukuba tsu...
6 篇 university of ch...
6 篇 department of el...
6 篇 univ warwick sch...
6 篇 xilinx inc san j...
5 篇 univ manchester ...
5 篇 department of el...
5 篇 univ toronto dep...
5 篇 inesc-id univers...
5 篇 swiss fed inst t...
5 篇 department of el...

作者

31 篇 luk wayne
21 篇 maruyama tsutomu
16 篇 koch dirk
14 篇 wayne luk
12 篇 wilton steven j....
12 篇 ienne paolo
11 篇 betz vaughn
10 篇 fahmy suhaib a.
10 篇 cheung peter y. ...
9 篇 vaughn betz
9 篇 constantinides g...
9 篇 prasanna viktor ...
9 篇 amano hideharu
8 篇 paolo ienne
8 篇 chow paul
8 篇 akash kumar
7 篇 kapre nachiket
7 篇 teich juergen
7 篇 suhaib a. fahmy
7 篇 alonso gustavo

语言

1,898 篇 英文
8 篇 其他
4 篇 中文

检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

共 1910 条记录，以下是451-460 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

An FPGA-based Hardware Accelerator for Scene Text Character Recognition 26

An FPGA-based Hardware Accelerator for Scene Text Character ...

引用

26th IFIP/IEEE international conference on Very Large Scale Integration, VLSI-SoC 2018

作者： De Oliveira, Luiz Antonio Barros, Edna Centro de Informática Universidade Federal de Pernambuco Recife Brazil

ISBN: (纸本)9781538647561

Scene text character recognition is a challenging task in Computer Vision since natural scene images usually have cluttered background and the character's size, font, orientation, texture, brightness, and alignment in the picture are variable and non-predictable. Furthermore, most systems including scene text character recognition are usually embedded in a system on a chip (SoC), which has critical requirements, such as low latency, low area, mobility, and flexibility, at the same time that they require high accuracy. In this context, in this work we propose a heterogeneous system for embedded applications with time, area and power constraints, that combines hardware and software to accelerate a technique for scene text character recognition, based on Histogram of Oriented Gradients (HOG) for feature extraction and a neural network Extreme Learning Machine (ELM) as a classifier. the system was prototyped and experimented in the Terasic embedded platform DE2i-150 and the results showed that the system has accuracy of 65.5% in the Chars74k-15 dataset and is able to process up to 11 frames per second, having a good trade-off between processing time and accuracy in embedded environments. Moreover, it occupies only 11% logic elements of the Altera Cyclone IV FPGA, enabling its use in embedded systems. © 2018 IEEE.

关键词： field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

the Monte Carlo PUF 27

The Monte Carlo PUF

引用

27th international conference on field programmable logic and applications (FPL)

作者： Rozic, Vladimir Yang, Bohan Vliegen, Jo Mentens, Nele Verbauwhede, Ingrid Katholieke Univ Leuven COSIC Kasteelpk Arenberg 10 B-3001 Leuven Heverlee Belgium

ISBN: (纸本)9789090304281

Physically unclonable functions are used for IP protection, hardware authentication and supply chain security. While many PUF constructions have been put forward in the past decade, only few of them are applicable to FPGA platforms. Strict constraints on the placement and routing are the main disadvantages of the existing PUFs on FPGAs, because they place a high effort on the designer. In this paper we propose a new delay-based PUF construction called Monte Carlo PUF, that does not require low-level placement and routing control. this construction relies on the on-chip Monte Carlo method that is applied for measuring the delays of logic elements in order to extract a unique device fingerprint. the proposed construction allows a trade-off between the evaluation time and the error rate. the Monte Carlo PUF is implemented and evaluated on Xilinx Spartan-6 FPGAs.

关键词： Monte Carlo methods Delays field programmable gate arrays Delay lines Radiation detectors Ring oscillators Security

来源：评论

学校读者我要写书评

暂无评论

Accelerating Low Bit-Width Convolutional Neural Networks With Embedded FPGA 27

Accelerating Low Bit-Width Convolutional Neural Networks Wit...

引用

27th international conference on field programmable logic and applications (FPL)

作者： Jiao, Li Luo, Cheng Cao, Wei Zhou, Xuegong Wang, Lingli Fudan Univ State Key Lab ASIC & Syst Shanghai Peoples R China

ISBN: (纸本)9789090304281

Convolutional Neural Networks (CNNs) can achieve high classification accuracy while they require complex computation. Binarized Neural Networks (BNNs) with binarized weights and activations can simplify computation but suffer from obvious accuracy loss. In this paper, low bit-width CNNs, BNNs and standard CNNs are compared to show that low bit-width CNNs is better suited for embedded systems. An architecture based on the two-stage arithmetic unit (TSAU) as the basic processing element is proposed to process each layer iteratively for low bit-width CNN accelerators. then the DoReFa-Net which is trained with weights and activations represented in 1 bit and 2 bits respectively is implemented on Zynq XC7Z020 FPGA with a 410.2 GOPS performance. the accelerator can meet the real-time requirement of embedded applications with a 106 FPS throughput and a 73.1% top-5 accuracy on the ImageNet dataset. the accelerator outperforms existing FPGA-based CNN accelerators in the tradeoff among accuracy, energy and resource efficiency.

关键词： Kernel field programmable gate arrays Table lookup Neural networks Computational modeling Quantization (signal) Convolution

来源：评论

学校读者我要写书评

暂无评论

Scalable Inference of Decision Tree Ensembles: Flexible Design for CPU-FPGA Platforms 27

Scalable Inference of Decision Tree Ensembles: Flexible Desi...

引用

27th international conference on field programmable logic and applications (FPL)

作者： Owaida, Muhsen Zhang, Hantian Zhang, Ce Alonso, Gustavo ETH Syst Grp Dept Comp Sci Zurich Switzerland

ISBN: (纸本)9789090304281

Decision tree ensembles are commonly used in a wide range of applications and becoming the de facto algorithm for decision tree based classifiers. Different trees in an ensemble can be processed in parallel during tree inference, making them a suitable use case for FPGAs. Large tree ensembles, however, require careful mapping of trees to on-chip memory and management of memory accesses. As a result, existing FPGA solutions suffer from the inability to scale beyond tens of trees and lack the flexibility to support different tree ensembles. In this paper we present an FPGA tree ensemble classifier together with a software driver to efficiently manage the FPGA's memory resources. the classifier architecture efficiently utilizes the FPGA's resources to fit half a million tree nodes in on-chip memory, delivering up to 20x speedup over a 10-threaded CPU implementation when fully processing the tree ensemble on the FPGA. It can also combine the CPU and FPGA to scale to tree ensembles that do not fit in on-chip memory, achieving up to an order of magnitude speedup compared to a pure CPU implementation. In addition, the classifier architecture can be programmed at runtime to process varying tree ensemble sizes.

关键词： field programmable gate arrays Decision trees Vegetation Memory management Engines Layout

来源：评论

学校读者我要写书评

暂无评论

doppioDB: A Hardware Accelerated Database 27

doppioDB: A Hardware Accelerated Database

引用

27th international conference on field programmable logic and applications (FPL)

作者： Sidler, David Owaida, Muhsen Istvan, Zsolt Kara, Kaan Alonso, Gustavo Swiss Fed Inst Technol Dept Comp Sci Syst Grp Zurich Switzerland

ISBN: (纸本)9789090304281

Relational databases provide a wealth of functionality to a wide range of applications. Yet, there are tasks for which they are less than optimal, for instance when processing becomes more complex (e.g., regular expression evaluation, data analytics) or the data is less structured (e.g., text or long strings). With the increasing amount of user-generated data stored in relational databases, there is a growing need to analyze unstructured text data. At the same time more complex analytical operators are required to extract useful information from the vast amount of collected data. However, many analytical operators incur a significant compute complexity not suitable to database engines where multiple queries share the available resources. In this demonstration we show the benefit of using specialized hardware for such tasks and highlight the importance of a flexible, reusable mechanism for extending database engines with hardware-based operators. Our hybrid database engine, doppioDB, is deployed on an emerging Xeon+FPGA multicore architecture where the CPU and FPGA have cache-coherent access to the same memory, such that the hardware operators can directly access the database tables. the demonstration is illustrating the acceleration benefits of hardware operators, as well as doppioDB's flexibility in accommodating changing workloads.

关键词： Hardware Acceleration Databases field programmable gate arrays Engines Software

来源：评论

学校读者我要写书评

暂无评论

Latency-Driven Design for FPGA-based Convolutional Neural Networks 27

Latency-Driven Design for FPGA-based Convolutional Neural Ne...

引用

27th international conference on field programmable logic and applications (FPL)

作者： Venieris, Stylianos I. Bouganis, Christos-Savvas Imperial Coll London Dept Elect & Elect Engn London England

ISBN: (纸本)9789090304281

In recent years, Convolutional Neural Networks (ConvNets) have become the quintessential component of several state-of-the-art Artificial Intelligence tasks. Across the spectrum of applications, the performance needs vary significantly, from high-throughput image recognition to the very low-latency requirements of autonomous cars. In this context, FPGAs can provide a potential platform that can be optimally configured based on different performance requirements. However, with the increasing complexity of ConvNet models, the architectural design space becomes overwhelmingly large, asking for principled design flows that address the application-level needs. this paper presents a latency-driven design methodology for mapping ConvNets on FPGAs. the proposed design flow employs novel transformations over a Synchronous Dataflow-based modelling framework together with a latency-centric optimisation procedure in order to efficiently explore the design space targeting low-latency designs. Quantitative evaluation shows large improvements in latency when latency-driven optimisation is in place yielding designs that improve the latency of AlexNet by 73.54x and VGG16 by 5.61x over throughput-optimised designs.

关键词： field programmable gate arrays Feature extraction Space exploration Computational modeling Machine learning Convolution Biological system modeling

来源：评论

学校读者我要写书评

暂无评论

A Partial Reconfiguration based Microphone Array Network Emulator 27

A Partial Reconfiguration based Microphone Array Network Emu...

引用

27th international conference on field programmable logic and applications (FPL)

作者： da Silva, Bruno Dominguez, Federico Braeken, An Touhafi, Abdellah Vrije Univ Brussel Dept Ind Sci INDI Brussels Belgium Escuela Super Politecn Litoral ESPOL Guayaquil Ecuador

ISBN: (纸本)9789090304281

Nowadays, microphone arrays are used in many applications for sound-source localization or acoustic enhancement. the current Micro-Electro-Mechanical Systems (MEMS) technology allows the development of networks of microphone arrays at a relatively low cost. Unfortunately, the evaluation of these networks requires controlled acoustic environments, such as anechoic chambers, to avoid possible distortions and acoustic artifacts. In this paper, we present a partial reconfigurable FPGA platform to emulate a network of microphone arrays. Our platform provides a controlled simulated acoustic environment, able to evaluate the impact of different network configurations such as the number of microphones per array, the network's topology or the used detection method. Data fusion techniques, combining the data collected by each node, are used in this platform. In addition, our platform is also capable to converge to the ideal network with regards to power consumption, while still maintaining the desired level of sound-source localization accuracy. A graphical user interface provides a friendly control of the network and the parameters under test during the execution of the partial reconfiguration operations. Several experiments are presented to demonstrate some of the capabilities of our platform.

关键词： field programmable gate arrays Microphone arrays Acoustics Data integration Computer architecture Acoustic arrays

来源：评论

学校读者我要写书评

暂无评论

REAPR: Reconfigurable Engine for Automata Processing 27

REAPR: Reconfigurable Engine for Automata Processing

引用

27th international conference on field programmable logic and applications (FPL)

作者： Xie, Ted Dang, Vinh Wadden, Jack Skadron, Kevin Stan, Mircea Univ Virginia Dept Elect & Comp Engn Charlottesville VA 22903 USA Univ Virginia Dept Comp Sci Charlottesville VA 22903 USA

ISBN: (纸本)9789090304281

Finite automata have proven their usefulness in high-profile domains ranging from network security to machine learning. While prior work focused on their applicability for purely regular expression workloads such as antivirus and network security rulesets, recent research has shown that automata can optimize the performance for algorithms in other areas such as machine learning and even particle physics. Unfortunately, their emulation on traditional CPU architectures is fundamentally slow and further bottlenecked by memory. In this paper, we present REAPR: Reconfigurable Engine for Automata PRocessing, a flexible framework that synthesizes RTL for automata processing applications as well as I/O to handle data transfer to and from the kernel. We show that even with memory and control flow overheads, FPGAs still enable extremely high-throughput computation of automata workloads compared to other architectures.

关键词： Automata field programmable gate arrays Engines Learning automata Benchmark testing Computer architecture

来源：评论

学校读者我要写书评

暂无评论

Versatile Deployment of FPGA Accelerators in Disaggregated Data Centers: a Bioinformatics Case Study 27

Versatile Deployment of FPGA Accelerators in Disaggregated D...

引用

27th international conference on field programmable logic and applications (FPL)

作者： Alachiotis, Nikolaos theodoropoulos, Dimitris Pnevmatikatos, Dionisios Fdn Res & Technol Hellas Inst Comp Sci Iraklion 70013 Greece Tech Univ Crete Sch Elect & Comp Engn Khania 73100 Greece

ISBN: (纸本)9789090304281

Important design considerations for the cost-effective employment of hardware accelerators in next-generation data centers involve a) the type of candidate applications that a proposed solution can accelerate (generality), and b) the required development effort to successfully deploy the available accelerators for a given application (adoption overhead). To address the problem of generality, we present a versatile and dynamically reconfigurable hardware architecture that exhibits several accelerator slots and programmable interconnect to create application-specific accelerator datapaths. the proposed architecture fits in the model of disaggregated data centers, where compute, memory, and accelerators are broadly regarded as large pools of resources, and subsets of these resource pools are dynamically allocated on an as-needed basis to cooperatively boost performance of a broad range of applications. Initial results for a bioinformatics application that we employ as a case study and deals with the detection of positive selection in large-scale genomic datasets reveal a speedup of up to 6.4X when custom hardware accelerators are mapped to the proposed versatile accelerator architecture and compared with a parallel and highly optimized software implementation executed on a multi-core processor.

关键词： Hardware Acceleration Computer architecture field programmable gate arrays Genomics Bioinformatics

来源：评论

学校读者我要写书评

暂无评论

Vivado Design Interface: An Export/Import Capability for Vivado FPGA Designs 27

Vivado Design Interface: An Export/Import Capability for Viv...

引用

27th international conference on field programmable logic and applications (FPL)

作者： Townsend, thomas Nelson, Brent Brigham Young Univ Dept Elect & Comp Engn NSF Ctr High Performance Reconfigurable Comp CHRE Provo UT 84602 USA

ISBN: (纸本)9789090304281

Research tools targeting commercial FPGAs have most commonly been based on the Xilinx Design Language (XDL). Vivado, however, does not support XDL, preventing similar tools from being created for next-generation devices. Instead, Vivado includes a Tcl interface that exposes Xilinx's internal design and device data structures. Considerable challenges still remain to users attempting to leverage this Tcl interface to develop external CAD tools. this paper presents the Vivado Design Interface (VDI), a set of file formats and Tcl functions that address the challenges of exporting and importing designs to and from Vivado. To demonstrate its use, VDI has been integrated with RapidSmith2, an external FPGA CAD framework. To our knowledge this work is the first successful attempt to provide an open-source tool-flow that can export designs from Vivado, manipulate them with external CAD tools, and re-import an equivalent representation back into Vivado.

关键词： Tools Computer architecture Routing Microprocessors field programmable gate arrays Pins Wires

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共191页 << < 42 43 44 45 46 47 48 49 50 51 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：