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Decision Tree Based Hardware Power Monitoring for Run Time Dynamic Power Management in FPGA 27

Decision Tree Based Hardware Power Monitoring for Run Time D...

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27th international conference on field programmable logic and applications (FPL)

作者： Lin, Zhe Zhang, Wei Sharad, Sinha Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Hong Kong Peoples R China Nanyang Technol Univ Sch Comp Engn Singapore Singapore

ISBN: (纸本)9789090304281

Fine-grained runtime power management techniques could be promising solutions for power reduction. therefore, it is essential to establish accurate power monitoring schemes to obtain dynamic power variation in a short period (i.e., tens or hundreds of clock cycles). In this paper, we leverage a decision-tree-based power modeling approach to establish fine-grained hardware power monitoring on FPGA platforms. A generic and complete design flow is developed to implement the decision tree power model which is capable of precisely estimating dynamic power in a fine-grained manner. A flexible architecture of the hardware power monitoring is proposed, which can be instrumented in any RTL design for runtime power estimation, dispensing with the need for extra power measurement devices. Experimental results of applying the proposed model to benchmarks with different resource types reveal an average error up to 4% for dynamic power estimation. Moreover, the overheads of area, power and performance incurred by the power monitoring circuitry are extremely low. Finally, we apply our power monitoring technique to the power management using phase shedding with an on-chip multi-phase regulator as a proof of concept and the results demonstrate 14% efficiency enhancement for the power supply of the FPGA internal logic.

关键词： Decision trees Monitoring field programmable gate arrays Estimation Runtime Feature extraction Hardware

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A Fair and Comprehensive Large-Scale Analysis of Oscillation-Based PUFs for FPGAs 27

A Fair and Comprehensive Large-Scale Analysis of Oscillation...

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27th international conference on field programmable logic and applications (FPL)

作者： Wild, Alexander Becker, Georg T. Gueneysu, Tim NXP Semicond Eindhoven Netherlands ESMT Berlin Digital Soc Inst Berlin Germany Univ Bremen Bremen Germany

ISBN: (纸本)9789090304281

Physical Unclonable Functions (PUFs) have gained a lot of research attention in recent years resulting in many different PUF proposals. Several of these proposals were aimed specifically at FPGA implementations. However, often these PUFs are evaluated and implemented for different (and often old) FPGA families with different metrics. Missing implementation details in many papers further hamper a fair analysis, as small details such as the exact routing can have significant impact on the PUF performance. In this paper we aim to overcome these problems by providing a fair comparison of some of the most promising Weak PUFs for FPGAs, the classic Ring Oscillator PUF (RO PUF), the Loop PUF and the TERO PUF. Each PUF is implemented with the same area optimizations and careful manual routing for modern Xilinx Artix-7 FPGAs and several implementation options are discussed. We measure the reliability and uniqueness of the PUF constructs on 100 BASYS-3 boards for a temperature range of -22 degrees C to 44 degrees C and use a glitch-generating core to analyze the vulnerability of the PUF constructs to surrounding logic. Our results show that the RO PUF has the best reliability in the presence of temperature variations while TERO has the best uniqueness of the three considered PUFs. Interestingly, the TERO PUF also shows the highest resistance to surrounding logic. To encourage further research in FPGA PUFs and to enable a fair comparison to future work the implementations as well as the measurement data will be made publicly available.

关键词： Physical Unclonable Function (PUF) Ring Oscillator PUF TERO PUF Loop PUF field programmable Gate Array (FPGA)

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Reliable SEU Monitoring and Recovery using a programmable Configuration Controller 27

Reliable SEU Monitoring and Recovery using a Programmable Co...

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27th international conference on field programmable logic and applications (FPL)

作者： Gong, Lingkan Kroh, Alexander Agiakatsikas, Dimitris Nguyen, Nguyen T. H. Cetin, Ediz Diessel, Oliver UNSW Sydney Sch Comp Sci & Engn Sydney NSW Australia UNSW Sydney Sch Elect Engn & Telecommun Sydney NSW Australia Macquarie Univ Dept Engn N Ryde NSW Australia

ISBN: (纸本)9789090304281

FPGAs are promising candidates for computational tasks in space. However, they are susceptible to radiation-induced errors in their configuration memory. the recovery of configuration errors, either by device scrubbing or by module-based recovery, involves a series of reads and writes to the FPGA's configuration port, and is efficiently performed on-chip by a fast, flexible and reliable reconfiguration controller. In this work, we consider the reliability improvement of the recently proposed programmable Configuration Controller (PCC), a soft reconfiguration controller that has been shown to be both fast and flexible, but whose reliability, particularly in the face of radiation-induced configuration errors, has not until now been studied. To ensure that the PCC itself is reliable, we propose the use of traditional Triple Modular Redundant (TMR) combined with a novel software-based interrupt-driven fault recovery process that leverages hardware-accelerated configuration access. We report on our design space exploration to balance the utilization, error recovery performance, and reliability of the PCC. In extremely harsh radiation environments, the Mean Time to Failure of the PCC is as high as 25 years, compared with 3.5 hours for its non-protected counterpart, and that it takes as little as 27 ms to recover from a configuration memory error affecting the PCC.

关键词： field programmable gate arrays Tunneling magnetoresistance Synchronization Registers Reliability engineering Performance evaluation

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Find the Real Speed Limit: FPGA CAD for Chip-Specific Application Delay Measurement 27

Find the Real Speed Limit: FPGA CAD for Chip-Specific Applic...

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27th international conference on field programmable logic and applications (FPL)

作者： Ahmed, Ibrahim Zhao, Shuze Trescases, Olivier Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9789090304281

Process variation is increasing with each successive technology node, and it has reached the point where the worst-case timing modelling employed by current FPGA CAD tools is significantly underutilizing the available silicon. Previous studies have proposed exploiting FPGA reconfigurability to reduce this underutilization using techniques such as late binding and dynamic voltage scaling. Most of the proposed solutions require the ability to measure the target application's delay on each configured chip. To accurately measure the delay of an application on a certain chip, we must measure the delay of its speed limiting paths on this specific chip. In this paper, we present a variation-aware CAD tool that automatically generates calibration bitstreams to measure the delay of any input application. Our tool identifies the statistically critical paths of the circuit and optimally selects which paths to test such that it minimizes the chances of reporting an optimistic delay, under a constraint on the number of allowed calibration bitstreams. Experimental results across a suite of benchmarks show that with one calibration bitstream we achieve 16x lower probability of reporting an optimistic delay compared to a greedy approach. With three calibration bitstreams, we reduce the probability of optimism to two chips in a million, approximately 6,000x lower than a greedy approach.

关键词： Delays Table lookup Calibration Semiconductor device measurement Integrated circuit modeling Computational modeling field programmable gate arrays

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Accelerating In-System FPGA Debug of High-Level Synthesis Circuits using Incremental Compilation Techniques 27

Accelerating In-System FPGA Debug of High-Level Synthesis Ci...

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27th international conference on field programmable logic and applications (FPL)

作者： Bussa, Pavan Kumar Goeders, Jeffrey Wilton, Steven J. E. Univ British Columbia Dept Elect & Comp Engn Vancouver BC Canada Brigham Young Univ Dept Elect & Comp Engn Provo UT 84602 USA

ISBN: (纸本)9789090304281

High-Level Synthesis has emerged as a promising technology for improving FPGA designer productivity, but will only be successful if it is accompanied by a debug ecosystem. Recent efforts have presented in-system debug techniques which allow a designer to debug an implementation, running on an FPGA, in the context of the original source code. these techniques typically store a history of all user variables on chip. To maximize the effectiveness of the on-chip memory, it is desirable to store only selected user variables. Unfortunately, this may lead to multiple debug runs. In existing frameworks, changing the variables to be stored between runs requires a full recompile. In this paper, we propose several flows that use incremental compilation to reduce the debug turn-around time. the first flow, in which the user circuit and instrumentation are co-optimized during compilation, gives the fastest debug clock speeds but suffers in user circuit performance once the debug instrumentation is removed. In the second flow, the optimization of the user circuit is sacrosanct. It is placed and routed first without having any constraints and the debug instrumentation is added later leading to the fastest user circuit clock speeds, but performance suffers slightly during debug. Using either flow, we achieve 40% reduction in debug turn-around times, on average.

关键词： Instruments field programmable gate arrays Debugging History Tools Hardware System-on-chip

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Scalable High-Performance Architecture for Convolutional Ternary Neural Networks on FPGA 27

Scalable High-Performance Architecture for Convolutional Ter...

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27th international conference on field programmable logic and applications (FPL)

作者： Prost-Boucle, Adrien Bourge, Alban Petrot, Frederic Alemdar, Hande Caldwell, Nicholas Leroy, Vincent Univ Grenoble Alpes CNRS Grenoble INP TIMAInst Engn F-38000 Grenoble France Univ Grenoble Alpes CNRS Grenoble INP LIGInst Engn F-38000 Grenoble France

ISBN: (纸本)9789090304281

thanks to their excellent performances on typical artificial intelligence problems, deep neural networks have drawn a lot of interest lately. However, this comes at the cost of large computational needs and high power consumption. Benefiting from high precision at acceptable hardware cost on these difficult problems is a challenge. To address it, we advocate the use of ternary neural networks (TNN) that, when properly trained, can reach results close to the state of the art using floating-point arithmetic. We present a highly versatile FPGA friendly architecture for TNN in which we can vary both the number of bits of the input data and the level of parallelism at synthesis time, allowing to trade throughput for hardware resources and power consumption. To demonstrate the efficiency of our proposal, we implement high-complexity convolutional neural networks on the Xilinx Virtex-7 VC709 FPGA board. While reaching a better accuracy than comparable designs, we can target either high throughput or low power. We measure a throughput up to 27000 fps at approximate to 7 W or up to 8.36 TMAC/s at approximate to 13 W.

关键词： Neurons Parallel processing Random access memory field programmable gate arrays Hardware throughput Neural networks

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Bridging High-Level Synthesis and Application-Specific Arithmetic: the Case Study of Floating-Point Summations 27

Bridging High-Level Synthesis and Application-Specific Arith...

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27th international conference on field programmable logic and applications (FPL)

作者： Uguen, Yohann de Dinechin, Florent Derrien, Steven Univ Lyon INSA Lyon Inria CITI F-69621 Villeurbanne France Univ Rennes 1 IRISA Rennes France

ISBN: (纸本)9789090304281

FPGAs are well known for their ability to perform non-standard computations not supported by classical microprocessors. Many libraries of highly customizable application-specific IPs have exploited this capablity. However, using such IPs usually requires handcrafted HDL, hence significant design efforts. High Level Synthesis (HLS) lowers the design effort thanks to the use of C/C++ dialects for programming FPGAs. However, high-level C language becomes a hindrance when one wants to express non-standard computations: this languages was designed for programming microprocessors and carries with it many restrictions due to this paradigm. this is especially true when computing with floating-point, whose data-types and evaluation semantics are defined by the IEEE-754 and C11 standards. If the high-level specification was a computation on the reals, then HLS imposes a very restricted implementation space. this work attempts to bridge FPGA application-specific efficiency and HLS ease of use. It specifically targets the ubiquitous floating-point summation-reduction pattern. A source-to-source compiler transforms selected floating-point additions into sequences of simpler operators using non-standard arithmetic formats. this improves performance and accuracy for several benchmarks, while keeping the ease of use of a high-level C description.

关键词： field programmable gate arrays Hardware Tools Open area test sites Adders Program processors Optimization

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Heterogeneous Virtualized Network Function Framework for the Data Center 27

Heterogeneous Virtualized Network Function Framework for the...

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27th international conference on field programmable logic and applications (FPL)

作者： Tarafdar, Naif Lin, thomas Eskandari, Nariman Lion, David Leon-Garcia, Alberto Chow, Paul Univ Toronto Toronto ON Canada

ISBN: (纸本)9789090304281

We present a framework for creating heterogeneous virtualized network function (VNF) service chains from cloud data center resources. Traditionally, these functions are packaged in software images within a catalog of networking applications that can be loaded onto a virtual machine CPU, and can be offered to users as a service. Our framework combines the best of both software and hardware by allowing users to chain traditional software-based VNFs with hardware-based VNFs that the user provides as an IP to generate a bitstream or a pre-generated VNF as part of a library. To accomplish this, our framework first creates the hardware bitstreams and programs the FPGA VNFs, loads any software VNFs requested, and programs the network to daisy chain the VNFs together. Furthermore, this enables an incremental design flow where the user can start by implementing a chain of VNFs in software and incrementally substitute software VNFs for their hardware counterparts. Our paper investigates two case studies to show the ability to switch between hardware and software VNFs in our framework and to demonstrate the benefit of using hardware VNFs. the first study is signature matching at fixed offsets, similar to matching packet headers. In this case study, the CPU can keep up at line-rate using specialized networking drivers. the second case study involves string matching within a packet, which requires scanning through the entire frame. In this case, the CPU performance drops to approximately 20 percent of the input rate, whereas the FPGA can continue to keep up at line-rate.

关键词： field programmable gate arrays Virtual machining Hardware Cloud computing IP networks

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Customizing Low-Precision Deep Neural Networks for FPGAs

Customizing Low-Precision Deep Neural Networks for FPGAs

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international conference on field programmable logic and applications

作者： Julian Faraone Giulio Gambardella David Boland Nicholas Fraser Michaela Blott Philip H.W. Leong The University Of Sydney Xilinx Research Labs

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685181

In this paper, we argue that instead of solely focusing on developing efficient architectures to accelerate well-known low-precision CNNs, we should also seek to modify the network to suit the FPGA. We develop a fully automative toolflow which focuses on modifying the network through filter pruning, such that it efficiently utilizes the FPGA hardware whilst satisfying a predefined accuracy threshold. Although fewer weights are re-moved in comparison to traditional pruning techniques designed for software implementations, the overall model complexity and feature map storage is greatly reduced. We implement the AlexNet and TinyYolo networks on the large-scale ImageNet and PascalVOC datasets, to demonstrate up to roughly 2× speedup in frames per second and 2× reduction in resource requirements over the original network, with equal or improved accuracy.

关键词： field programmable gate arrays Hardware Quantization (signal) throughput Memory management Neural networks

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Tile Size Selection for Optimized Memory Reuse in High-Level Synthesis 27

Tile Size Selection for Optimized Memory Reuse in High-Level...

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27th international conference on field programmable logic and applications (FPL)

作者： Liu, Junyi Wickerson, John Constantinides, George A. Imperial Coll London Dept Elect & Elect Engn London SW7 2AZ England

ISBN: (纸本)9789090304281

High-level synthesis (HLS) is well capable of generating control and computation circuits for FPGA accelerators, but still requires sufficient human effort to tackle the challenge of memory and communication bottlenecks. One important approach for improving data locality is to apply loop tiling on memory-intensive loops. Loop tiling is a well-known compiler technique that partitions the iteration space of a loop nest into chunks (or 'tiles') whose associated data can fit into size-constrained fast memory. the size of the tiles, which can significantly affect the memory requirement, is usually determined by partial enumeration. In this paper, we propose an analytical methodology to select a tile size for optimized memory reuse in HLS. A parametric polyhedral model is introduced to capture memory usage analytically for arbitrary tile sizes. To determine the tile size for data reuse in constrained on-chip memory, an algorithm is then developed to optimize over this model, using non-linear solvers to minimize communication overhead. Experimental results on three representative loops show that, compared to random enumeration with the same time budget, our proposed method can produce tile sizes that lead to a 75% average reduction in communication overhead. A case study with real hardware prototyping also demonstrates the benefits of using the proposed tile size selection.

关键词： System-on-chip Memory management field programmable gate arrays Arrays Silicon Random access memory Data models

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