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检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

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FPGA-Based Accelerator for Model Predictive Control of Induction Motor Drive

FPGA-Based Accelerator for Model Predictive Control of Induc...

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MECHATRONIKA international Symposium

作者： Tomas Kosan Jakub Talla Stepan Janous Vojtech Blahnik Regional Innovation Centre for Electrical Engineering University of West Bohemia Pilsen Czech Republic Department of Electromechanics and Power Electronics University of West Bohemia Pilsen Czech Republic

ISBN: (纸本)9781538643648;9788021455429

the model predictive control is a set of algorithms which uses the dynamical model of controlled system to predict the future systems responses. Nowadays, the nonlinear finite control set model predictive control (FCS-MPC) is a popular technique for control of induction motor drives. the FCS-MPC enables accurate and high-dynamic control of the induction motor currents, rotational speed, torque etc. with respect to system constraints (e.g. current/voltage limitations). the main drawbacks of FCS-MPC algorithms are their computational requirements which reduce FCS-MPC prediction horizon and its applications. Our paper is focused on the FPGA accelerator of FCS-MPC of induction motor extended by the three phase inverter model with dead-times and voltage drops. these inverter nonlinear effects play important role especially in non-nominal drive conditions (e.g. low speeds).

关键词： Inverters Generators field programmable gate arrays Induction motors Pulse width modulation Computational modeling Mathematical model

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Enabling Partial Reconfiguration and Low Latency Routing using Segmented FPGA NoCs 27

Enabling Partial Reconfiguration and Low Latency Routing usi...

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27th international conference on field programmable logic and applications (FPL)

作者： Vipin, Kizhepatt Gray, Jan Kapre, Nachiket Mahindra Ecole Cent Hyderabad Telangana India Gray Res LLC Bellevue WA USA Univ Waterloo Waterloo ON Canada

ISBN: (纸本)9789090304281

Deflection-routed FPGA overlay NoCs such as Hoplite suffer from high worst-case routing latencies due to the penalty of deflections at large system sizes. Segmentation of communication channels in such NoCs can (I) reduce worstcase packet routing latencies for FPGA traffic, (2) enable efficient composition of multi-application NoC workloads, and (3) ease the burden of supporting Partial Reconfiguration (PR) for FPGAs. We use segmentation of the NoC links by inserting isolation multiplexers along NoC links to split traffic into different regions. this segmentation reduces routing latencies by localizing the deflected packets to stay within the segmented region. this can be done either statically using configuration bits that can be changed per application phase approximate to 1000s of cycles or completely dynamically on a per-cycle basis based on packet addresses. For the Xilinx VC709 FPGA board, we build an 8x8 deflection-routed NoC, with 4x4 statically fracturable regions having 256b-wide links with 6% extra LUT resources and no extra pipelining cost to support fracturing while running at >200 MHz. We comprehensively outperform the CONNECT Torus NoC by 2-3x across various traffic patterns while using 4-7x less FPGA resources. When considering real-world traffic extracted from Sniper simulations of multi-processor PARSEC benchmarks, we observe up to 2.7x improvement in throughput for 8x8 NoC with static segmentation. With fully dynamic segmentation applied to large 30 x 7 NoC with 300b links, hosting a 1,680-core parallel processor, segmenting the NoC into six 5 x 7 segments uses an additional 1% of device LUTs but improves throughput by as much as 2.5 x for LOCAL traffic.

关键词： field programmable gate arrays Routing Multiplexing Switches Table lookup Fabrics Electronic mail

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Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs

Lite-CNN: A High-Performance Architecture to Execute CNNs in...

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international conference on field programmable logic and applications

作者： Mário Véstias Rui Policarpo Duarte José T. de Sousa Horácio Neto INESC-ID ISEL Instituto Politecnico de Lisboa INESC-ID Universidade de Lisboa Portugal Inst. Super. Tecnico Universidade de Lisboa Lisboa Lisboa PT

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685181

Due to the computational complexity of Convolutional Neural Networks (CNNs), high performance platforms are generally considered for their execution. However, CNNs are very useful in embedded systems and its execution right next to the source of data has many advantages, like avoiding the need for data communication. In this paper, we propose an architecture for CNN inference (Lite-CNN) that can achieve high performance in low density FPGAs. Lite-CNN adopts a fixed-point representation for both neurons and weights, which was already shown to be sufficient for most CNNs. Also, with a simple and known dot product reorganization, the number of multiplications is reduced to half. We show implementation results for 8 bit fixed-point in a ZYNQ7020 and extrapolate for other larger FPGAs. Lite-CNN achieves 410 GOPs in a ZYNQ7020.

关键词： Neurons Kernel field programmable gate arrays Convolution three-dimensional displays Computer architecture Mathematical model

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A Zero-Timing Overhead SET Mitigation Approach for Flash-based FPGAs

A Zero-Timing Overhead SET Mitigation Approach for Flash-bas...

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European conference on Radiation and its Effects on Components and Systems (RADECS)

作者： Sarah Azimi Boyang Du Luca Sterpone Politecnico di Torino Torino Italy

ISBN: (数字)9781728102160

ISBN: (纸本)9781728102177

Reliability of Integrated Circuits (ICs) is nowadays a major concern for sub-micron technologies especially when they are adopted in mission critical applications. the decreasing of device feature size leads to an increasing of the device sensitivity against Single Event Effects (SEEs), especially Single Event Transients (SETs), induced particle strikes within the device silicon structure. Flash-based FPGA is a golden core for aerospace safety critical applications; however, traditional SET mitigation solutions, such as filter insertion, can lead to performance degradation of the implemented design. In this paper, we provide a new implementation flow that is able to evaluate the SET phenomena considering its specific convergence case and effectively mitigate the SETs without introducing any performance penalization to the original netlist. Experimental results on different sets of benchmark circuits demonstrated the mitigation of SET events without affecting the timing performances of the circuits.

关键词： field programmable gate arrays logic gates Routing Delays Benchmark testing Tools Filtering

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A State Machine Block for High-Level Synthesis 16

A State Machine Block for High-Level Synthesis

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16th IEEE international conference on field-programmable Technology (ICFPT)

作者： Assadikhomami, Shadi Ongko, Jennifer Aamodt, Tor M. Univ British Columbia Dept Elect & Comp Engn Vancouver BC Canada

ISBN: (纸本)9781538626566

FPGAs are being deployed in datacenters to enable improved energy efficiency and application acceleration. this paper explores whether FPGA designs can be improved to make them more effective in this new role. We explore the properties of applications after high-level synthesis has been applied and note that for irregular applications, a large fraction of FPGA resources may be consumed implementing finite state machines. For many applications the resulting state machines have states with a single successor and limited fan-out degree. We propose a mixed-grained logic block architecture exploiting these properties that can be integrated into current FPGA architectures, which reduces the area of the next state calculation in FSMs by more than 3x in average without impacting performance.

关键词： field programmable gate arrays Encoding Registers Random access memory Tools Metadata Benchmark testing

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Accelerating MPI Message Matching through FPGA Offload

Accelerating MPI Message Matching through FPGA Offload

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international conference on field programmable logic and applications

作者： Qingqing Xiong Anthony Skjellum Martin C. Herbordt Boston University Boston MA USA Boston University Chattanooga TN USA Dept..of Electr. & Comput. Eng. Boston Univ. Boston MA USA

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685181

the Message Passing Interface (MPI) is the de facto communication standard for distributed-memory High-Performance Computing (HPC) systems. Ultra-low latency communication in HPC is difficult to achieve because of MPI processing requirements, in particular matching requests and messages done by traversing the corresponding queues. Many researchers have addressed this issue by redesigning queues or by offloading them to hardware accelerators. However, state-of-art software approaches cannot free CPUs “from the misery” and hardware approaches either lack scalability or still leave substantial room for further improvement. With the emergence of numerous tightly coupled CPU-FPGA computing architectures, offload of MPI functionality to user-controlled hardware is now becoming viable; we find it productive to revisit hardware approaches. To maintain the generality necessary to support MPI while preventing high resource utilization, we design our MPI queue processing offload based on a recent analysis of performance characteristics in HPC applications. We propose a novel, two-level message queue design: a content addressable memory (CAM) coupled with a resource-saving hardware linked-list. We also propose an optimization that maintains high speed in the cases when the queue is long. To test our design, we create an SOC-based testbed consisting of softcore processors and hardware implementations of the MPI communication stacks. Even while using only a small fraction of the Stratix-V logic, our design can be one to two orders of magnitude faster than two well-known hardware designs.

关键词： Hardware field programmable gate arrays Program processors Queueing analysis Acceleration Scalability

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An Actor-Based Runtime Monitoring System for Web and Desktop applications 18

An Actor-Based Runtime Monitoring System for Web and Desktop...

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18th IEEE/ACIS international conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD)

作者： Lavery, Paul Watanabe, Takuo Tokyo Inst Technol Dept Comp Sci Meguro Ku 2-12-1 Ookayama Tokyo 1528552 Japan

ISBN: (纸本)9781509055043

In this paper, we introduce a runtime monitoring method for Actor-based programs and present a Scala module that realizes the proposed method. the primary characteristic of our method is that it supports asynchronous message-passing based on the Actor model. Besides, the module does not require specialized languages for describing application properties to be monitored. Once a developer incorporates the module in his/her application, it continuously checks whether the application satisfies certain properties described as Scala code and invokes mitigation code when it finds the violation of the properties. this paper also provides two non-trivial use cases to illustrate how the module can be seamlessly integrated into actual modern Scala applications. We also demonstrate the efficiency of the module using a set of benchmarks that resulted in only 8% of the experiments causing more than 5% runtime overhead.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Acceleration of solving quadratic assignment problems on programmable soc using high level synthesis 4

Acceleration of solving quadratic assignment problems on pro...

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international Workshop on FPGAs for Software Programmers, FSP 2017, co-located with international conference on field programmable logic and applications, FPL 2017

作者： Kanazawa, Kenji Faculty of Engineering Information and Systems University of Tsukuba 1-1-1 Ten-ou-dai Tsukuba Ibaraki Japan

ISBN: (纸本)9783800744435

the quadratic assignment problem (QAP) is an NP-hard combinatorial optimization problem with various real-world applications. Breakout local search (BLS) is among the best performing heuristic algorithms to solve QAPs. BLS uses an adaptive perturbation mechanism to escape from local minima that complicates the control structure of BLS while BLS involves an abundance of data-level parallelism. In this paper, we propose a hardware solver for QAP on Xilinx Zynq-MPSoC. Zynq is a programmable SoC that consists of an ARM microprocessor and a programmable logic fabric that are tightly coupled on the same chip, and developed based on a software design by using High-level synthesis. Our proposed approach leverages inherent parallelism in BLS while maintaining the algorithmic behavior and control structure in the original software design, and outperforms software execution of BLS, parallel execution of BLS on a multicore CPU, and previous accelerators on GPU. © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： Software design

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A case for better integration of host and target compilation when using Open CL for FPGAS 4

A case for better integration of host and target compilation...

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international Workshop on FPGAs for Software Programmers, FSP 2017, co-located with international conference on field programmable logic and applications, FPL 2017

作者： Lloyd, Taylor Chikin, Artem Ochoa, Erick Ali, Karim Amaral, José Nelson University of Alberta Edmonton Canada

ISBN: (纸本)9783800744435

Major field-programmable Gate Array (FPGA) vendors, such as Intel and Xilinx, provide toolchains for compiling Open Computing Language (OpenCL) to FPGAs. However, the separate host and device compilation approach advocated by OpenCL hides compiler optimization opportunities that can dramatically improve FPGA performance. this paper demonstrates the advantages of combined host and device compilation for OpenCL on FPGAs by presenting a series of transformations that require inter-compiler communication. Further, because of extremely long FPGA synthesis times, the overhead of recompiling the host code for each compilation of FPGA kernel code is relatively inexpensive. Our transformations are integrated with the Intel FPGA SDK for OpenCL and are evaluated on a subset of the Rodinia benchmark suite using an Altera Stratix V FPGA. © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： field programmable gate arrays (FPGA)

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Xilinx FPGA Based Single Phase Five-Level Cascaded Z-Source Inverter

Xilinx FPGA Based Single Phase Five-Level Cascaded Z-Source ...

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India international conference on Power Electronics (IICPE)

作者： Jammy Ramesh Rahul A. Kirubakaran Department of Electrical Engineering National Institute of Technology Warangal Warangal

ISBN: (纸本)9781538649978;9781538649961

this paper presents a single phase five-level cascaded Z-source inverter with reduced number of switches for PV/FC/Wind power applications. the inherent benefits of z-source inverter are higher boost gain and fault ride through capability compared with the traditional VSI and CSI inverters. therefore five-level Z-source converter is simulated in MATLAB/Simulink environment and the generation of control pulses with the help of Xilinx System Generator is presented. A prototype model is developed to validate the theoretical concepts through experimental and simulation results.

关键词： Inverters field programmable gate arrays Matlab Mathematical model Generators Modulation logic gates

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