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Tectogrammatical Trees and Fuzzy Natural logic in Linguistic Characterization of Dynamic Processes 17

Tectogrammatical Trees and Fuzzy Natural Logic in Linguistic...

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Joint 17th World Congress of international-Fuzzy-Systems-Association / 9th international conference on Soft Computing and Intelligent Systems (IFSA-SCIS)

作者： Novak, Vilem Univ Ostrava Inst Res & Applicat Fuzzy Modeling NSC IT4Innovat 30Dubna 22 Ostrava 70103 1 Czech Republic

ISBN: (纸本)9781509049172

this paper is a contribution to the applications of fuzzy logic in modeling of linguistic semantics. the topic of interest is description of the past course of a dynamical process that is given by data in the form of time series. We suggest to use the well developed technique of linguistic theory, the so called tectogrammatical trees using which linguists represent semantics of sentences. the core of the suggested procedure is construction of the tectogrammatical tree that is then assigned a formula of fuzzy natural logic. As the latter construes semantics of the given sentence, we can construct a model on the basis of the given data. If successful, the initial sentence can be taken as a linguistic characterization of them. In this paper we demonstrate how sentences characterizing the course of the trend of time series can be assigned the formulas of fuzzy natural logic expressing their semantics via tectogrammatical trees.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Spatial memory trace prediction 4

Spatial memory trace prediction

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international Workshop on FPGAs for Software Programmers, FSP 2017, co-located with international conference on field programmable logic and applications, FPL 2017

作者： Gebara, Nadeen Yassir Ienne, Paolo Fleming, Kermin Intel Corporation HudsonMA United States EPFL Lausanne Switzerland

ISBN: (纸本)9783800744435

Heterogeneous FPGA systems among other spatial architectures are gaining popularity as candidates for accelerating Data Center and HPC applications. As the number of FLOPs supported on FPGAs increases, the rate at which data can be provided to computational units becomes the major bottleneck determining overall system performance. this heightens the importance of having a quick way to observe and understand the memory access patterns of applications on FPGAs prior to investing long periods of time and effort in writing RTL, especially for applications that will not observe any performance improvements due to bandwidth limitations. Furthermore, since the memory subsystem within FPGAs is programmable, a clear visibility of the spatial memory access patterns of applications prior to design implementation can guide FPGA programmers on the best way to configure and use the memory subsystem in an application specific manner while providing an estimate of bandwidth requirements. In this paper, we present a novel approach for obtaining memory traces of workloads targeting FPGA systems to provide insight on the memory access patterns of applications and guide FPGA programmers. Our algorithm displays an average prediction accuracy of 97.45% for read memory accesses when RTL optimization opportunities are fully exploited, and an accuracy of 90.71% for memory write accesses across the investigated benchmarks. By providing a fast and efficient way to obtain spatial memory reference traces of applications, our work not only guides FPGA programmers by providing more insight into the memory profiles of workload regions amenable to FPGA implementations, but also helps leverage the shortage of memory traces available for performing architectural studies and enhancing FPGA memory systems. © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： field programmable gate arrays (FPGA)

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Implementation and Optimization of throughput in High Speed Memory Interface Using AXI Protocol

Implementation and Optimization of Throughput in High Speed ...

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international conference on Computing and Networking Technology (ICCNT)

作者： C Sarojini Jaisingh thangaraj Dept of Electronics engineering IIT(ISM) Dhanbad India

the current challenge is to meet out the compatibility of data rates between the data processing systems and the memory bandwidth requirements. For a stream oriented data, Double Data Rate Type three (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) memory interface boosts the buffering capability for processing applications. In this paper, We mainly focus on optimizing the throughput of a high speed DDR3 memory interface using the Advanced eXtensible Interface (AXI) protocol containing independent read/write channels. We have designed the user defined logic in the AXI master to command the AXI slave viz., DDR3 memory. the final design is implemented in the Microsemi RTG4 series FPGA and operated at the frequency of 320 MHz. the design is articulated to achieve maximum throughput by designing AXI master without write response states.

关键词： throughput Clocks Protocols field programmable gate arrays Bandwidth IP networks Random access memory

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Accelerating linux bash commands on FPGAS using partial reconfiguration 4

Accelerating linux bash commands on FPGAS using partial reco...

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international Workshop on FPGAs for Software Programmers, FSP 2017, co-located with international conference on field programmable logic and applications, FPL 2017

作者： Horta, Edson Shen, Xinzi Pham, Khoa Koch, Dirk School of Computer Science University of Manchester United Kingdom

ISBN: (纸本)9783800744435

the Linux Operating System is used by a wide range of companies, mainly due to its security and stability. the latest FPGA devices, with embedded processors, allow the development of SoCs running this OS. One of the key features of FPGAs is their ability to change the hardware architecture while the system is running. It is possible to reconfigure one or more regions of the FPGA while the remainder continues to work. these partially reconfigurable regions inside the FPGA can be used to implement software functions, accelerating the execution time for the system. this work presents an FPGA system that provides the required interfaces to deploy Linux bash commands mapped directly into partially reconfigurable blocks of the FPGA. these commands can be executed in any order, thanks to a hardware interface, equivalent to the software pipe interface in Linux, implemented on the static region of the FPGA. the methodology presented in this paper allows the hardware implementations of commands that can be directly interfaced to the std_in and std_out inside the FPGA. this integration is executed in a very flexible manner according to the currently called bash command. this approach can be used to improve the performance of Linux applications through the use of hardware accelerated bash commands. Moreover, this approach is providing a template that will make hardware and software integration very easy. © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： field programmable gate arrays (FPGA)

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An IP Core Integration Tool-Flow for Prototyping Software-Defined Radios using Static Dataflow with Access Patterns 16

An IP Core Integration Tool-Flow for Prototyping Software-De...

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16th IEEE international conference on field-programmable Technology (ICFPT)

作者： Tsoeunyane, Lekhobola J. Winberg, Simon Inggs, Michael Univ Cape Town Software Defined Radio Grp Dept Elect Engn Cape Town South Africa

ISBN: (纸本)9781538626566

the current design practices for prototyping Software Defined Radio (SDR) applications using reconfigurable FPGA platforms often rely on the reuse of Intellectual Property (IP) processing cores. this design practice usually involves stitching together these IP blocks to formulate a working system. High-level Synthesis (HLS) tools that support IP core integration often do not fully allow for capturing critical application timing constraints nor provide mechanisms to automatically adjust integrating logic to maintain these constraints. Consequently, reusing IP cores tends to involve many manual and time-consuming design tasks, often at a low level of abstraction. Moreover, these tasks may need to be repeated during the development process. To address these problems, we present a new open tool-flow, built upon the Delite compiler infrastructure. Central to our tool-flow is an automated mechanism for interconnecting a selection of IP cores that maintain particular application timing constraints. A crucial part of our approach and the focus of this paper is the way this tool-flow uses a static dataflow with access patterns (SDF-AP) model to efficiently capture precise timing for aspects of the processing chain. We demonstrate the capability of our tool-flow by generating six typical SDR applications in VHDL. We show how slight modifications to a design, which would have previously needed many manual adjustments, can be carried out quickly using this tool-flow. To evaluate our tool-flow, we compare performance and area results of our tool-generated SDR designs with equivalent hand-coded designs. We found that the generated solutions closely match the results obtained from our hand-coded designs, showing merit for our approach. Our plans for future work include refining the tool-flow, further optimizing the generated code, and performance testing of a wider range of SDR applications.

关键词： field programmable gate arrays Tools Timing DSL Clocks Ports (Computers) Analytical models

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Security by Design in System on a Chip applications 12

Security by Design in System on a Chip Applications

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12th international conference on Cyber Warfare and Security (ICCWS)

作者： Reber, Patrick Graham, Scott Air Force Inst Technol Wright Patterson AFB OH 45433 USA

ISBN: (纸本)9781911218265

System on a Chip (SoC) devices pairing a field programmable Gate Array (FPGA) and a processor on a single chip have grown in popularity and capability since their introduction in 2011, while decreasing in power-consumption and cost. Offering considerable benefits, including shorter development time to market and increased flexibility, these devices continue to capture market share, including medical, military, automotive, and control system applications. Security is essential due to the safety critical nature of these applications. In addition to physical security of these devices, designers must be able to secure the software they run. External interfaces provide malicious actors an attack surface to alter the software executed on the processor or semi-permanently alter the FPGA functionality via remote reprogramming. We contend that the security against both of these threats is permanently influenced by initial design decisions, including configuration modes and data storage choices. Alternatively, configuration mode choices may allow for integrity checking of all boot stages as well as application memory of running programs, reducing security threats. the flexibility offered by SoCs increases this trade space between security, flexibility, integrity, cost, and simplicity. Designers incorporating SoCs into their systems must be informed of these trade-offs to ensure future security of their applications. Previous publications on design guidance focus on capabilities and implementation details without addressing system-level security decisions. these documents aid engineers in how to implement features, but lack advice on meeting security goals. this paper helps to evaluate the security requirements and recommends varied levels of protections.

关键词： FPGA system on a chip attestation programmable logic control security

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DC-DC Boost Converter Stability with Constant Power Load

DC-DC Boost Converter Stability with Constant Power Load

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IEEE international conference on Power Electronics and Motion Control

作者： Mohammed Kh. Al-Nussairi Ramazan Bayindir Department of Electrical and Electronic Engineering Gazi University Ankara Turkey

In this paper, the fuzzy logic control (FLC) is presented to address the instability effects of constant power load, and how to regulate the output voltage of a DC-DC Boost converter. the constant power load has negative incremental resistance, which makes the system unstable under a small disturbance on the load. To evaluate the performance, the proposed method is simulated by a MATLAB-SIMULINK model. Furthermore, the proposed concept is validated experimentally using a field programmable gate Array FPGA-Based Hardware-in-the-Loop Simulation by hardware description language.

关键词： Dc-dc boost converter Constant power load Incremental negative resistance Fuzzy logic controller FPGA-in-Loop

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SPynq: Acceleration of Machine Learning applications over Spark on Pynq 17

SPynq: Acceleration of Machine Learning Applications over Sp...

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17th Annual international conference on Embedded Computer Systems - Architectures, Modeling, and Simulation (SAMOS)

作者： Kachris, Christoforos Koromilas, Elias Stamelos, Ioannis Soudris, Dimitrios NTUA Inst Commun & Comp Syst ICCS Athens Greece Natl Tech Univ Athens Dept Elect & Comp Engn Athens Greece

ISBN: (纸本)9781538634370

Spark is one of the most widely used frameworks for data analytics that offers fast development of applications like machine learning and graph computations in distributed systems. In this paper, we present SPynq: A framework for the efficient utilization of hardware accelerators over the Spark framework on heterogeneous MPSoC FPGAs, such as Zynq. Spark has been mapped to the Pynq platform and the proposed framework allows the seamlessly utilization of the programmable logic for the hardware acceleration of computational intensive Spark kernels. We have also developed the required libraries in Spark that hides the accelerator's details to minimize the design effort to utilize the accelerators. A cluster of 4 nodes (workers) based on the all-programmable MPSoCs has been implemented and the proposed platform is evaluated in a typical machine learning application based on logistic regression. the logistic regression kernel has been developed as an accelerator and incorporated to the Spark. the developed system is compared to a high-performance Xeon cluster that is typically used in cloud computing. the performance evaluation shows that the heterogeneous accelerator-based MpSoC can achieve up to 2.3x system speedup compared with a Xeon system (with 90% accuracy) and 20x better energy-efficiency. For embedded application, the proposed system can achieve up to 40x speedup compared to the software only implementation on low-power embedded processors and 30x lower energy consumption.

关键词： Sparks Hardware Program processors Libraries Machine learning field programmable gate arrays Cloud computing field programmable gate arrays Program processors sparks Cloud Computing Computer hardware Artificial Intelligence Machine Learning Libraries Accelerators design effort Performance Evaluation hardware accelerator

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Benzimidazole/reduced graphene oxide based field effect transistor for mercury ion detection in water

Benzimidazole/reduced graphene oxide based field effect tran...

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international conference on Emerging Electronics (ICEE)

作者： S Ramakrishnan Damini V Kumar H Nagarajaiah S Saravanan Praveen C Ramamurthy Department of Materials Engineering Indian Institute of Science Bangalore India

Benzimidazole based derivate [2-(4,7di(thiophen-2-yl)-1H-benzo[d]imidazol-2-yl)-6hydroxymethyl)-4methylphenol (BI) modified reduced graphene oxide (BI-RGO) was prepared by simple noncovalent functionalization. Analytical spectroscopy by (Fourier transform infrared, UV-Visible and Raman) revealed the modification has occurred by RGO with BI through π-π interaction. the Photoluminescence spectrum shows that BIRGO has 18% quenching compared to neat BI derivatives. UV-Visible and PL Spectrum reveals the electronic and optical properties of the BI and the changes that occurs after functionalization. Raman and FTIR spectrum of the compounds also revealed the presence of different functional groups and structural configuration. RGO and RGO-BI which provides all the details for further study regarding sensor applications.

关键词： Ions Metals Graphene Scanning electron microscopy Vibrations field effect transistors logic gates

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Implementation and Optimization of the Accelerator Based on FPGA Hardware for LSTM Network 15

Implementation and Optimization of the Accelerator Based on ...

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15th IEEE international Symposium on Parallel and Distributed Processing with applications (ISPA) / 16th IEEE international conference on Ubiquitous Computing and Communications (IUCC)

作者： Zhang, Yiwei Wang, Chao Gong, Lei Lu, Yuntao Sun, Fan Xu, Chongchong Li, Xi Zhou, Xuehai USTC Dept Comp Sci & Technol Hefei 230027 Anhui Peoples R China USTC Suzhou Inst Adv Study Suzhou Peoples R China

ISBN: (纸本)9781538637906

Today, artificial neural networks (ANNs) are important machine learning methods which are widely used in a variety of applications. As the emerging field of ANNs, recurrent neural networks (RNNs) are often used for sequence-related applications. And Long Short-Term Memory (LSTM) is an improved RNN which contains complex computational logic. To achieve high accuracy, researchers always build large-scale LSTM networks which are time-consuming and power-consuming. thus the acceleration of LSTM networks, low power & energy consumption become the hot issues in today's research. In this paper, we present a hardware accelerator for the LSTM neural network layer based on FPGA Zedboard and use pipeline methods to parallelize the forward computing process. To optimize our implementation, we also use multiple methods including tiled matrix-vector multiplication, binary adder tree, and overlap of computation and data access. through the acceleration and optimization methods, our accelerator is power-efficient and has a better performance than ARM Cortex A9 processor and Intel Core i5 processor.

关键词： field programmable gate arrays Adders Pipelines Vegetation Hardware Acceleration Computer architecture

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