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检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

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25th international conference on field programmable logic and applications, FPL 2015

25th International Conference on Field Programmable Logic an...

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25th international conference on field programmable logic and applications, FPL 2015

ISBN: (纸本)9780993428005

the proceedings contain 97 papers. the topics discussed include: using island-style bi-directional intra-CLB routing in low power FPGAs;energy efficient partitioning of dynamic reconfigurable MRAM-FPGAs;automatic support for multi-module parallelism from computational patterns;fine-tuning CLB placement to speed up reconfigurations in NVM-based FPGAs;a technology mapper for depth-constrained FPGA logic cells;parallel feature extraction and heterogeneous object-detection for multi-camera driver assistance systems;generating FPGA accelerators for chemical similarity assessment;7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2;NetFPGA - rapid prototyping of high bandwidth devices in open source;optimizing energy efficient low-swing interconnect for sub-threshold FPGAs;reduction calculater in an FPGA based switching hub for high performance clusters;and serial and parallel interleaved modular multipliers on FPGA platform.

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Design and FPGA Implementation of a Fuzzy-PI Controller for Omnidirectional Robot System 4th

Design and FPGA Implementation of a Fuzzy-PI Controller for ...

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4th international conference on Robot Intelligence Technology and applications (RiTA)

作者： Masmoudi, Mohamed Slim Krichen, Najla Koesdwiady, Arief B. Karray, Fakhri Masmoudi, Mohamed Natl Sch Elect & Commun Sfax METS Res Grp TechnopkBP 1163CP 3018 Sfax Tunisia Natl Engineers Sch Sfax CEM Lab BP 3000 Sfax Tunisia Univ Waterloo Ctr Pattern Anal & Machine Intelligence Waterloo ON Canada Natl Engineers Sch Sfax METS Res Grp Tunisia Route SoukraKm 3-5BP 1173 Sfax 3038 Tunisia

ISBN: (纸本)9783319312934;9783319312910

Fuzzy logic systems have been implemented successfully for the design of a wide variety of control systems. they provide a powerful way for designing nonlinear controllers using human expert knowledge. In this article, we present an approach to design and implement a fuzzy logic proportional integral controller (Fuzzy-PI) for omnidirectional robot navigation system, using a field-programmable gate array (FPGA). First, we define the kinematic model of the robot system and then we design, simulate, and optimize the controller navigation system using MATLAB and Robot-ino Sim platforms. the main goal of this work is the design of the Fuzzy-PI controller and the hardware implementation using FPGA resources. the controller can be implemented on an FPGA using software or hardware approach. For the latter approach, the Fuzzy-PI algorithm is implemented in VHDL language, synthesized, optimized, placed and routed, and downloaded on an FPGA board.

关键词： Fuzzy logic

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A novel Κ convention logic (NCL) gates architecture based on basic gates 24

A novel Κ convention logic (NCL) gates architecture based o...

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24th IEEE international Congress on Electronics, Electrical Engineering and Computing, INTERCON 2017

作者： Oliveira, Duarte L. Verducci, Orlando Faria, Lester A. Curtinhas, Tiago Electronic Engineering Division Technological Institute of Aeronautics - ITA - IEEA Brazil

ISBN: (纸本)9781509063628

Digital circuit design may demand critical requirements, such as power consumption, robustness, performance, etc., while being implemented in VLSI (Very Large Scale Integration). the asynchronous paradigm presents interesting features that serve as an alternative to these critical requirements. An important class of the asynchronous paradigm is the one called QDI (Quasi Delay Insensitive) circuits that can also be used for critical requirements design. QDI circuits are interesting for these applications because they are robust to certain kinds of faults, to noise and to temperature and supply voltage variations, having also low electromagnetic emissions. An interesting style of QDI circuits is the NCL (Κ Convention logic) circuits because they accept conventional Boolean functions and can achieve great optimization. this paper presents an architecture based on basic QDI gates for the synthesis of NCL gates focusing on VLSI that uses only standard libraries and FPGA (field programmable Gate Array). © 2017 IEEE.

关键词： VLSI circuits

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Hardware Acceleration of Bayesian Neural Networks using RAM based Linear Feedback Gaussian Random Number Generators 35

Hardware Acceleration of Bayesian Neural Networks using RAM ...

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35th IEEE international conference on Computer Design (ICCD)

作者： Cai, Ruizhe Ren, Ao Wang, Luhao Pedram, Massoud Wang, Yanzhi Syracuse Univ Dept Elect Engn & Comp Sci Syracuse NY 13244 USA Univ Southern Calif Dept Elect Engn Los Angeles CA 90089 USA

ISBN: (纸本)9781538622544

Bayesian neural networks (BNNs) have been proposed to address the problem of model uncertainty in training. By introducing weights associated with conditioned probability distributions, BNN is capable to resolve overfitting issues commonly seen in conventional neural networks. Frequent usage of Gaussian random variables requires a properly optimized Gaussian Random Number Generator (GRNG). the high hardware cost of conventional GRNG makes the hardware realization of BNN challenging. In this paper, a new hardware acceleration architecture for variational inference in BNNs is proposed to facilitate the applicability of BNN in larger-scale applications. In addition, the proposed implementation introduced the RAM based Linear Feedback based GRNG (RLF-GRNG) for effective weight sampling in BNNs. the RAM based Linear Feedback method can effectively utilize RAM resources for parallel Gaussian random number generation while requiring limited and sharable control logic. Implementation on an Altera Cyclone V FPGA suggests that the RLF-GRNG utilizes much less RAM resources compared to other GRNG methods. Experiments results show that the proposed hardware implementation of a BNN can still attain similar accuracy compared to software implementation.

关键词： Hardware Neural networks Bayes methods Random access memory field programmable gate arrays Training Software

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"All programmable FPGA, providing hardware efficiency to software programmers"

"All programmable FPGA, providing hardware efficiency to sof...

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international conference on field programmable logic and applications

作者： Ivo Bolsens Xilinx

Smart Systems create new challenges for semiconductor components that need to provide, at one hand, the ease of software programmability and, on the other hand, the capability of hardware efficiency. this dichotomy is driven by, on the one hand, the need for a software stack that supports flexibility, scalability, fast development cycles and, on the other hand, the need for hardware optimization to support performance, efficiency and cost. In this talk, we will discuss the technical trends in major market segments such as datacenters, 5G wireless infrastructure and software defined networking and the resulting requirements for semiconductor platforms, both from hardware and software perspective. To provide an answer to these challenges, it will be demonstrated on how FPGA technology is evolving from a programmable hardware solution catering to ASIC refugees towards an All programmable architecture empowering system and software engineers.

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Parallel FPGA routing: Survey and challenges

Parallel FPGA routing: Survey and challenges

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international conference on field programmable logic and applications

作者： Mirjana Stojilović School of Computer and Communication Sciences Ecole Polytechnique Fédérale de Lausanne (EPFL) Switzerland

As transistor scaling is slowing down [1], other opportunities for ensuring continuous performance increase have to be explored. field programmable gate arrays (FPGAs) are in the spotlight these days: not only due to their malleability and energy efficiency, but also because FPGAs have recently been integrated into the cloud [2]. the latter makes them available to everyone in need of the immense computing power and data throughput they can offer. However, one important issue needs to be resolved first - the time to compile an industrial-scale design for an FPGA must be drastically reduced. Researchers have been looking for ways to accelerate FPGA routing through parallelism, since routing is one of the most time-consuming compilation steps. However, the ideal solution has not been found yet. this paper provides a survey of parallel FPGA routers, with the aim to identify their strengths and weaknesses, thus suggesting directions to take in further efforts for acceleration.

关键词： Routing field programmable gate arrays Program processors Message systems Acceleration Parallel processing Wires

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One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs

One size does not fit all: Implementation trade-offs for ite...

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international conference on field programmable logic and applications

作者： Gaël Deest Tomofumi Yuki Sanjay Rajopadhye Steven Derrien Univ. Rennes 1 / IRISA INRIA / IRISA Colorado State University

Iterative stencils are kernels in various application domains such as numerical simulations and medical imaging, that merit FPGA acceleration. the best architecture depends on many factors such as the target platform, off-chip memory bandwidth, problem size, and performance requirements. We generate a family of FPGA stencil accelerators targeting emerging System on Chip platforms, (e.g., Xilinx Zynq or Intel SoC). Our designs come with design knobs to explore trade-offs. We also propose performance models to hone in on the most interesting design points, and show how they accurately lead to optimal designs. the optimal choice depends on problem sizes and performance goals.

关键词： field programmable gate arrays System-on-chip Pipeline processing Memory management Acceleration Bandwidth Hardware

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the Monte Carlo PUF

The Monte Carlo PUF

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international conference on field programmable logic and applications

作者： Vladimir Rožić Bohan Yang Jo Vliegen Nele Mentens Ingrid Verbauwhede COSIC KU Leuven Leuven-Heverlee Belgium Katholieke Universiteit Leuven Leuven Flanders BE

Physically unclonable functions are used for IP protection, hardware authentication and supply chain security. While many PUF constructions have been put forward in the past decade, only few of them are applicable to FPGA platforms. Strict constraints on the placement and routing are the main disadvantages of the existing PUFs on FPGAs, because they place a high effort on the designer. In this paper we propose a new delay-based PUF construction called Monte Carlo PUF, that does not require low-level placement and routing control. this construction relies on the on-chip Monte Carlo method that is applied for measuring the delays of logic elements in order to extract a unique device fingerprint. the proposed construction allows a trade-off between the evaluation time and the error rate. the Monte Carlo PUF is implemented and evaluated on Xilinx Spartan-6 FPGAs.

关键词： Monte Carlo methods Delays field programmable gate arrays Delay lines Radiation detectors Ring oscillators Security

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Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAs

Generic and universal parallel matrix summation with a flexi...

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international conference on field programmable logic and applications

作者： thomas B. Preußer Technische Universitat Dresden Dresden Sachsen DE

Bit matrix compression is a highly relevant operation in computer arithmetic. Essentially being a multi-operand addition, it is the key operation behind fast multiplication and many higher-level operations such as multiply-accumulate, the computation of the dot product or the implementation of FIR filters. Compressor implementations have been constantly evolving for greater efficiency both in general and in the context of concrete applications or specific implementation technologies. this paper is building on this history and describes a generic implementation of a bit matrix compressor for Xilinx FPGAs, which does not require a generator tool. It contributes FPGA-oriented metrics for the evaluation of elementary parallel bit counters, a systematic analysis and partial decomposition of previously proposed counters and a fully implemented construction heuristic with a flexible compression target matching the device capabilities. the generic implementation is agnostic of the aspect ratio of the input matrix and can be used for multiplication the same way as it can be for single-column population count operations.

关键词： Radiation detectors Table lookup Adders field programmable gate arrays Measurement Sociology Statistics

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Line rate programmable packet processing in 100Gb networks

Line rate programmable packet processing in 100Gb networks

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international conference on field programmable logic and applications

作者： Pavel Benáček Viktor Puš Jan Kořenek Michal Kekely CESNET Prague6 Czech Republic Netcope Technologies Sochorova Brno Czech Republic

the P4 language provides a way to describe a custom network packet processing behavior that involves header parsing, matching and assembling modified packets. Such abstraction represents a significant step towards removing the limitation of fixed-function networking devices. Our live demonstration shows a straightforward usage of an algorithm and tool that maps a P4 program to a general architecture of FPGA-based networking device. Network traffic is received, parsed, filtered and modified by the generated circuit at the full line rate of 100 Gbps Ethernet. the results of our ongoing joint research project NFV200 show that the FPGA technology can be used to improve network flexibility without the usual burden of tedious and error-prone HDL coding.

关键词： field programmable gate arrays Protocols Pipeline processing Standards Software Tools Hardware design languages

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