检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,875 篇 会议
28 篇 期刊文献
7 册 图书

馆藏范围

1,910 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,242 篇 工学
- 1,040 篇 计算机科学与技术...
- 729 篇 软件工程
- 406 篇 电气工程
- 183 篇 电子科学与技术（可...
- 74 篇 信息与通信工程
- 63 篇 控制科学与工程
- 36 篇 仪器科学与技术
- 30 篇 机械工程
- 26 篇 动力工程及工程热...
- 23 篇 建筑学
- 17 篇 土木工程
- 15 篇 核科学与技术
- 13 篇 光学工程
- 13 篇 生物工程
- 10 篇 材料科学与工程（可...
- 10 篇 生物医学工程（可授...
- 8 篇 安全科学与工程
170 篇 理学
- 101 篇 数学
- 45 篇 物理学
- 18 篇 生物学
- 16 篇 系统科学
- 9 篇 统计学（可授理学、...
- 6 篇 化学
49 篇 管理学
- 38 篇 管理科学与工程(可...
- 19 篇 工商管理
- 14 篇 图书情报与档案管...
16 篇 医学
- 14 篇 临床医学
- 12 篇 特种医学
14 篇 法学
- 12 篇 社会学
9 篇 经济学
- 9 篇 应用经济学
5 篇 农学
5 篇 军事学
2 篇 教育学

主题

832 篇 field programmab...
688 篇 field programmab...
276 篇 hardware
156 篇 computer archite...
125 篇 logic gates
112 篇 table lookup
87 篇 throughput
87 篇 clocks
83 篇 random access me...
79 篇 routing
74 篇 software
72 篇 acceleration
65 篇 delays
65 篇 optimization
62 篇 kernel
54 篇 registers
54 篇 logic
50 篇 switches
49 篇 algorithm design...
47 篇 system-on-chip

机构

14 篇 univ toronto dep...
9 篇 imperial coll lo...
8 篇 school of comput...
8 篇 department of co...
8 篇 ecole polytech f...
7 篇 univ british col...
7 篇 brigham young un...
7 篇 imperial coll lo...
7 篇 tokyo inst techn...
6 篇 univ tsukuba tsu...
6 篇 university of ch...
6 篇 department of el...
6 篇 univ warwick sch...
6 篇 xilinx inc san j...
5 篇 univ manchester ...
5 篇 department of el...
5 篇 univ toronto dep...
5 篇 inesc-id univers...
5 篇 swiss fed inst t...
5 篇 department of el...

作者

31 篇 luk wayne
21 篇 maruyama tsutomu
16 篇 koch dirk
14 篇 wayne luk
12 篇 wilton steven j....
12 篇 ienne paolo
11 篇 betz vaughn
10 篇 fahmy suhaib a.
10 篇 cheung peter y. ...
9 篇 vaughn betz
9 篇 constantinides g...
9 篇 prasanna viktor ...
9 篇 amano hideharu
8 篇 paolo ienne
8 篇 chow paul
8 篇 akash kumar
7 篇 kapre nachiket
7 篇 teich juergen
7 篇 suhaib a. fahmy
7 篇 alonso gustavo

语言

1,898 篇 英文
8 篇 其他
4 篇 中文

检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

共 1910 条记录，以下是531-540 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

A dynamic partial reconfigurable overlay concept for PYNQ

A dynamic partial reconfigurable overlay concept for PYNQ

引用

international conference on field programmable logic and applications

作者： Benedikt Janßen Pascal Zimprich Michael Hübner Ruhr-Universitat Bochum Bochum Nordrhein-Westfalen DE Embedded Systems for Information Technology Ruhr-University Bochum Bochum Germany

Partial reconfiguration is a promising technique in the design of embedded systems since it enables an increase in efficiency and flexibility. However, its usage is still challenging due to the constraints of current FPGAs. In this paper, we present an extension of the Xilinx Python package `pynq' to ease the usage of partial reconfigurable bitstreams. the pynq package belongs to Xilinx's open source project PYNQ. the PYNQ project provides the Python language and its libraries to developers on the Xilinx Zynq. Our pynq package extension enables the usage of partial reconfigurable bitstreams. the concept is based on our Python package `pynqpartial'. this package can be integrated into an overlay for PYNQ to enable support for partial reconfigurable bitstreams. Our goal is to enable overlay developers to offer overlays which manage the partial reconfiguration transparent to the Python programmer. We evaluated our approach on the PYNQ-Z1.

关键词： Software field programmable gate arrays Tools Dictionaries Computer architecture Programming

来源：评论

学校读者我要写书评

暂无评论

Exploration of OpenCL for FPGAs using SDAccel and comparison to GPUs and multicore CPUs

Exploration of OpenCL for FPGAs using SDAccel and comparison...

引用

international conference on field programmable logic and applications

作者： Lester Kalms Diana Göhringer Technische Universität Dresden Dresden Germany

Due to energy efficiency, heterogeneous computing is gaining more and more attention. Since FPGA implementations are time consuming, high-level synthesis (HLS) is used to close the productivity gap. OpenCL has become accepted as a good programming model for HLS, due to its portability, good capability of design verification and rich instruction set. this work implements different optimization strategies using OpenCL for a heterogeneous system containing CPU, integrated GPU, GPU and FPGA. Energy efficiency and performance of the architectures are compared using a feature detection algorithm. It is shown how to maximize performance while hitting the maximum memory bandwidth and keeping the resource utilization low for the SDAccel tool from Xilinx. the evaluation shows the great streaming capability of OpenCL for FPGAs. the FPGA achieves a speed up of 62.8 and consumes 49 times less energy for the application in comparison to an optimized single threaded CPU implementation in full HD.

关键词： Kernel field programmable gate arrays Graphics processing units Bandwidth Optimization Resource management

来源：评论

学校读者我要写书评

暂无评论

Functional & timing in-hardware verification of FPGA-based designs using unit testing frameworks

Functional & timing in-hardware verification of FPGA-based d...

引用

international conference on field programmable logic and applications

作者： Julian Caba Fernando Rincoon Julio Daniel Dondo Department of Technology and Information Systems University of Castilla-La Mancha Spain Universidad de Castilla-La Mancha Ciudad Real Castilla-La Mancha ES

In this PhD dissertation, we propose a new testing approach for effectively managing hardware development risks, producing hardware designs with enough quality and reliability. Our proposal is based on the combination of high-level modelling and a unit testing framework in order to generate real hardware implementations for validating the designer intent, in order to keep a high cycle-accuracy and a low design effort. Such real hardware implementations are based on FPGAs, whose reconfigurability are key to provide a flexible verification environment, whereas unit testing frameworks have been extended to consider new testing requirements beyond pure functionality, such as timing analysis. Moreover, we provide a hardware library with two different types of components: 1) monitors to check internal variables at run time, keeping the errors to later trace them, and 2) double functions to reduce third-party dependencies.

关键词： Hardware Testing Timing field programmable gate arrays Tools Proposals Biological system modeling

来源：评论

学校读者我要写书评

暂无评论

Design of a Modular Multilevel Converter Prototype for Research Purposes

Design of a Modular Multilevel Converter Prototype for Resea...

引用

European conference on Power Electronics and applications

作者： Luca Bessegato Anant Narula Panagiotis Bakas Staffan Norrga KTH Royal Institute of Technology Stockholm Sweden Chalmers University of Technology Chalmers University of Technology Gothenburg Sweden

As modular multilevel converters gradually become the preferred topology for many high-voltage and high-power applications, they are widely studied among researchers, who need experimental results to validate their studies. this paper discusses the design of a down-scaled modular multilevel converter prototype for research purposes, equipped with 30 full-bridge submodules and 10 kW rating. the design of this prototype is aimed at safety, flexibility, orderliness, and compactness. the challenges posed by the implementation of the converter prototype are examined, discussing the design of the prototype structure, the communication scheme, the full-bridge submodules, and the control hierarchy. the control system is based on Xilinx Zynq system-on-chip, which integrates programmable logic and processing system, allowing for extensive computational capability as well as simple reconfiguration. Experimental results showing the prototype in operation at nominal ratings are presented along with the devised graphical user interface.

关键词： Multilevel converters Test bench field programmable Gate Array (FPGA) Measurement

来源：评论

学校读者我要写书评

暂无评论

Two-LUT-based synthesizable temperature sensor for Virtex-6 FPGA devices

Two-LUT-based synthesizable temperature sensor for Virtex-6 ...

引用

international conference on field programmable logic and applications

作者： Stephan Nolting Lin Liu Guillermo Payá-Vayá Institute of Microelectronic Systems Leibniz Universitä t Hannover Hannover Germany

this paper proposes a new synthesizable oscillator-based temperature sensor with minimal footprint for use in contemporary Xilinx FPGA devices. In contrast to previously published ring-oscillator architectures, based on inverters mapped onto single LUTs, the proposed oscillator uses an asynchronous Gray-coded 4-bit counter requiring only two 6-input LUTs. Due to its reduced hardware requirements, the feedback path can be implemented using local routing signals only. therefore, the impact of the routing on the oscillator frequency is slightly reduced making the oscillator less prone to placement-caused routing deviations. the proposed temperature sensor is calibrated using a two-point calibration approach, resulting in a mean accuracy of ±0.71° C with a mean resolution of 0.0081° C. As a further case study, a methodology to characterize on-chip semiconductor variations between identical FPGAs and within the same FPGA chip is presented using a sensor array, including up to 196 of the proposed two-LUT-based oscillators.

关键词： Oscillators Temperature sensors field programmable gate arrays Routing Table lookup Temperature measurement Radiation detectors

来源：评论

学校读者我要写书评

暂无评论

Parallel dot-products for deep learning on FPGA

Parallel dot-products for deep learning on FPGA

引用

international conference on field programmable logic and applications

作者： Mário Véstias Rui Policarpo Duarte José T. de Sousa Horácio Neto INESC-ID Instituto Politécnico de Lisboa INESC-ID Universidade de Lisboa Portugal

Deep neural networks have recently shown great results in a vast set of image applications. the associated deep learning models are computationally very demanding and, therefore, several hardware solutions have been proposed to accelerate their computation. FPGAs have recently shown very good performances for these kind of applications and so it is considered a promising platform to accelerate the execution of deep learning algorithms. A common operation in these algorithms is multiply-accumulate (MACC) that is used to calculate dot-products. Since many dot products can be calculated in parallel, as long as memory bandwidth is available, it is very important to implement this operation very efficiently to increase the density of MACC units in an FPGA. In this paper, we propose an implementation of parallel MACC units in FPGA for dot-product operations with very high performance/area ratios using a mix of DSP blocks and LUTs. We consider fixed-point representations with 8 bits of size, but the method can be applied to other bit widths. the method allows us to achieve TOPs performances, even for low cost FPGAs.

关键词： Digital signal processing Table lookup field programmable gate arrays Adders Machine learning Lead Bandwidth

来源：评论

学校读者我要写书评

暂无评论

Dynamic power estimation based on switching activity propagation

Dynamic power estimation based on switching activity propaga...

引用

international conference on field programmable logic and applications

作者： Y. Nasser J.-C. Prévotet Maryline Hélard J. Lorandel Institut national des sciences appliquées de Rennes INSA Rennes - IETR Rennes France ETIS CNRS Cergy-Pontoise France

A new power estimation approach based on the decomposition of a digital system into basic operators is presented. this approach aims to estimate the energy consumption at early design phases of digital blocks implemented on FPGAs. Each operator has its own model which estimates the switching activity and the power consumption. By interconnecting several operators, statistical information is then propagated to provide a global power estimation of a given system. A simple sum of the power dissipation contribution of each operator is enough to compute the total power consumption. this is performed by taking into account the switching activities relative to a given input pattern. Earlier, faster and more flexible power analysis for system designers are the advantages. this approach has been evaluated in a use-case application. the preliminary results indicate a promising speed-up of the design process and an error which is less than 8.0% compare to the classical power estimation tools.

关键词： Estimation Integrated circuit modeling field programmable gate arrays Switches Computational modeling Power demand Neural networks

来源：评论

学校读者我要写书评

暂无评论

Parallel RRT∗ architecture design for motion planning

Parallel RRT∗ architecture design for motion planning

引用

international conference on field programmable logic and applications

作者： Size Xiao Neil Bergmann Adam Postula School of Information Technology and Electrical Engineering The University of Queensland QLD Australia University of Queensland Brisbane QLD AU

A motion planning algorithm aims to calculate one obstacle-free trajectory which meets the dynamical constraints of a vehicle and leads the vehicle from the start state to the target state. RRT* (RRT star) is one sampling-based algorithm which is widely used in many applications because of its speed in quickly finding a trajectory. In contrast with basic RRT (Rapidly-exploring Random Trees) algorithm, RRT* improves trajectory optimality significantly by introducing the refinement step after setting up each tree node. this paper describes a new parallel version of the RRT* algorithm and its corresponding architecture on an FPGA (field programmable Gate Arrays). the refinement step is extracted and runs as a parallel process alongside a continuous tree-extending process. In order to avoid traversing all nodes in every iteration, tree nodes are stored in separate memory blocks and each block is assigned its own tree extending and refining pipelines to enhance the memory throughput. In the experimental evaluation, we take a 3-dimensional state spaces and implement the proposed architecture. the hardware implementation gives a 90 times speed improvement compared with an embedded software implementation, and a 30 times speedup compared to a desktop software implementation.

关键词： Computer architecture Pipelines Random access memory Algorithm design and analysis field programmable gate arrays Refining Planning

来源：评论

学校读者我要写书评

暂无评论

FPGA-Driven DAC with Second Order Sliding Mode Control of Filter Model for Hardware-In-the-Loop Simulators

FPGA-Driven DAC with Second Order Sliding Mode Control of Fi...

引用

IEEE international conference on Power Electronics and Motion Control

作者： Tamas Kokenyesi Marton Hegedus Szabolcs Vereb Attila Balogh Zoltan Suto Istvan Varjasi Department of Automation and Applied Informatics Budapest University of Technology and Economics

ISBN: (纸本)9781538641996

the advances in FPGA technology have enabled to develop fast HIL (Hardware-in-the-Loop) simulators, revolutionizing control software and hardware development for power electronics. HIL simulators should reproduce the same analogue signals that could be measured on real main circuits. A very common limitation in these applications is the usable pin count of the FPGA, therefore using the most pin-effective Digital-to-Analogue Converters (DACs) becomes critical. Σ-Δ DACs provide a simple, FPGA-synthesizable solution using a single pin for each output, but the output signal's bandwidth and latency is usually not sufficient, because of the required analogue filters. Higher order Σ-Δ DACs usually perform much better in the aspect of the Signal-to-Noise-Ratio (SNR) but not the usable bandwidth. this paper introduces a new bitstream DAC architecture based on the sliding mode control of the output analogue filter model. It is optimized mainly to reproduce current transducer signals in power electronics (usually triangle waves), which can be done more accurately than traditional Σ-Δ solutions.

关键词： Variable structure systems field programmable gate arrays Development Assistance Committee DERIVED AIR CONCENTRATION simulator HARDWARE IN thE LOOP Computer hardware Current transducers Power electronics high intensity lighting signal to noise ratios Output

来源：评论

学校读者我要写书评

暂无评论

doppioDB: A hardware accelerated database

doppioDB: A hardware accelerated database

引用

international conference on field programmable logic and applications

作者： David Sidler Muhsen Owaida Zsolt István Kaan Kara Gustavo Alonso Systems Group ETH Zürich

Relational databases provide a wealth of functionality to a wide range of applications. Yet, there are tasks for which they are less than optimal, for instance when processing becomes more complex (e.g., regular expression evaluation, data analytics) or the data is less structured (e.g., text or long strings). With the increasing amount of user-generated data stored in relational databases, there is a growing need to analyze unstructured text data. At the same time more complex analytical operators are required to extract useful information from the vast amount of collected data. However, many analytical operators incur a significant compute complexity not suitable to database engines where multiple queries share the available resources. In this demonstration we show the benefit of using specialized hardware for such tasks and highlight the importance of a flexible, reusable mechanism for extending database engines with hardware-based operators. Our hybrid database engine, doppioDB, is deployed on an emerging Xeon+FPGA multicore architecture where the CPU and FPGA have cache-coherent access to the same memory, such that the hardware operators can directly access the database tables. the demonstration is illustrating the acceleration benefits of hardware operators, as well as doppioDB's flexibility in accommodating changing workloads.

关键词： Hardware Acceleration Databases field programmable gate arrays Engines Software

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共191页 << < 50 51 52 53 54 55 56 57 58 59 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：