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检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

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Time-borrowing platform in the Xilinx UltraScale+ family of FPGAs and MPSoCs 26

Time-borrowing platform in the Xilinx UltraScale+ family of ...

引用

26th international conference on field-programmable logic and applications, FPL 2016

作者： Ganusov, Ilya Devlin, Benjamin Xilinx Inc. 2100 Logic Drive San JoseCA95124-3400 United States

ISBN: (纸本)9782839918442

this paper presents enhancements to the Xilinx UltraScale+ clocking architecture to support fine-grain time-borrowing. Time borrowing improves performance by redistributing timing slack between fast and slow paths. the Ultra-Scale+ architecture introduces programmable hardware delays and pulse generators embedded in the clocking tree to support time-borrowing based both on clock skew scheduling and pulsed latches. this programmable hardware allows borrowing from a few picoseconds to multiple nanoseconds between sequential pipeline stages without any changes to RTL, placement or routing. Vivado algorithms automatically determine when to skew flip-flop clock or convert them to pulsed latches to achieve the highest possible performance. Using the default Vivado flow, this programmable time-borrowing platform delivers 5.5% Fmax increase on average over a suite of 89 industrial designs. It is especially effective on high-speed applications, delivering up to 13.7% Fmax increase on individual designs. We also demonstrate that using non-default features, such as delays cascades or increasing hold margin, can increase average performance gains to 7.4% and 8.5%, respectively. this platform incurs minimum area (less than 0.1% of total chip area) while staying robust in the presence of tight hold constraints and increasing process variation. © 2016 EPFL.

关键词： field programmable gate arrays (FPGA)

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Model Checking Reconfigurable Petri Nets with Maude 9th

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9th international conference on Graph Transformation in Memory of Hartmut Ehrig (ICGT) held as part of conference on Software Technologies - applications and Foundations (STAF)

作者： Padberg, Julia Schulz, Alexander Hamburg Univ Appl Sci Hamburg Germany

ISBN: (纸本)9783319405308;9783319405292

Model checking is a widely used technique to prove properties such as liveness, deadlock or safety for a given model. Here we introduce model checking of reconfigurable Petri nets. these are Petri nets with a set of rules for changing the net dynamically. We obtain model checking by converting reconfigurable Petri nets to specific Maude modules and using then the LTLR model checker of Maude. the main result of this paper is the correctness of this conversion. We show that the corresponding labelled transitions systems are bisimular. In an ongoing example reconfigurable Petri nets are used to model and to verify partial dynamic reconfiguration of field programmable gate arrays.

关键词： Reconfigurable Petri nets Rewrite logic Maude Model checking field programmable gate array Dynamic partial reconfiguration

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High-speed Regular Expression Matching with Pipelined Automata 15

High-speed Regular Expression Matching with Pipelined Automa...

引用

15th international conference on field-programmable Technology (FPT)

作者： Matousek, Denis Korenek, Jan Pus, Viktor Brno Univ Technol Fac Informat Technol Bozetchova 1-2 Brno 61266 Czech Republic CESNET Ale Zikova 4 Prague 16000 Czech Republic

ISBN: (纸本)9781509056026

Pattern matching is a complex task which is widely used in network security monitoring applications. With the growing speed of network links, pattern matching architectures have to be improved in order to retain wire-speed processing. Multi-striding is a well-known technique on how to increase throughput of pattern matching architectures. In the paper we provide an analysis of scalability of multi-striding and show that it does not scale well and cannot be used for 100 Gbps throughput because utilization of FPGA resources grows exponentially. therefore, we have designed a new hardware architecture for high-speed pattern matching that combines the multi-striding technique and parallel processing using pipelined finite state machines (FSMs). the architecture shares a single packet buffer for all parallel FSMs. Efficient implementation of the packet buffer reduces the number of BlockRAMs to 18% when compared to simple parallel implementation. Instead of multiplexing input data, the architecture pipelines the states of FSMs. Such pipelined processing with only local communication has a direct positive impact on frequency and throughput and allows us to scale the architecture to hundreds of Gbps.

关键词： Automata throughput field programmable gate arrays Table lookup Random access memory Pattern matching

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Exploring Static and Dynamic Flash-based FPGA Design Topologies 34

Exploring Static and Dynamic Flash-based FPGA Design Topolog...

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34th IEEE international conference on Computer Design (ICCD)

作者： Abusultan, Monther Khatri, Sunil P. Texas A&M Univ ECE Dept College Stn TX 77843 USA

ISBN: (纸本)9781509051427

field programmable gate arrays (FPGAs) are the implementation platform of choice when it comes to design flexibility. However, SRAM-based FPGAs suffer from high power consumption, prolonged boot delays (due to the volatility of the configuration bits), and a significant area overhead (due to the use of 5T SRAM cells for the configuration bits). Floating gate (flash) based FPGAs can avert these problems. this paper presents a study of flash-based FPGA designs (both static and dynamic), and presents the tradeoff of delay, power dissipation and energy consumption of the various designs. Our work differs from previously proposed flash-based FPGAs, since we embed the flash transistors (which store the configuration bits) directly within the logic and interconnect fabrics. We also present a detailed description of how the programming of the configuration bits is accomplished. Our delay and power estimates are derived from circuit level simulations. Our proposed static flash-based LUT structure yields 10% faster operation, 12% lower dynamic power dissipation, 21% lower energy consumption and 29% lower static power dissipation compared to a traditional SRAM-based LUT. We also show that, for high performance applications, a dynamic flash-based LUT can achieve further performance improvements (32% lower delay) with higher energy consumption (37% higher) compared to an SRAM-based LUT. We also show that a flash-based interconnect structure provides 89% lower delay and 71% lower overall power consumption compared to the traditional interconnect structure used in SRAM-based FPGAs.

关键词： field programmable Gate Arrays Flash-based FPGA

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conference proceedings FPL 2016 [Table of contents]

Conference proceedings FPL 2016 [Table of contents]

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international conference on field programmable logic and applications

Presents the table of contents/splash page of the proceedings record.

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Applying Formal Verification to Early Assessment of FPGA-based Aerospace applications: Methodology and Experience 10

Applying Formal Verification to Early Assessment of FPGA-bas...

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10th Annual IEEE international Systems conference (SysCon)

作者： Hoque, Khaza Anuarul Mohamed, Otmane Ait Savaria, Yvon Concordia Univ Dept Elect & Comp Engn Montreal PQ Canada Polytech Montreal Dept Elect Engn Montreal PQ Canada

ISBN: (纸本)9781467395199

SRAM-based field programmable Gate Arrays (FPGAs) have been used in the aerospace application for more than a decade. Unfortunately, a significant disadvantage of these devices is their sensitivity to radiation effects that can cause bit flips in memory elements and ionisation induced faults in semiconductors, commonly known as Single Event Upsets (SEUs). An early dependability analysis on SRAM FPGA-based safety-critical application will enable the designers to develop a more reliable and robust design complying with design requirements, such as the DO-254 standard. We propose a methodology based on probabilistic model checking, to analyze the dependability and performability properties of such designs to guide design decisions. Probabilistic model checking is a well known formal verification technique, and the main advantage is that the analysis is exhaustive, which results in numerically exact answers to the temporal logic queries that contrast with discrete-event simulations. In the proposed methodology, starting from the high-level description of a system, a Markov (reward) model is constructed from the extracted Control Data Flow Graph (CDFG). Various dependability and performability related properties are then verified automatically using the PRISM model checker tool.

关键词： field programmable gate arrays (FPGA)

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A hardware/software codesign framework for vision-based ADAS

A hardware/software codesign framework for vision-based ADAS

引用

international conference on field programmable logic and applications

作者： Leandro Andrade Martinez Eduardo Marques Institute of Mathematics and Computer Sciences ICMC-USP São Carlos Brasil

this paper presents a framework for hardware and software co-design to building systems designed to driver assistant using computer vision. this work is part of a doctoral research project nearing completion. To valid... 详细信息

关键词： Hardware Web sites Software field programmable gate arrays Streaming media Computer vision Libraries

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FPGA-based implementation of sorting networks in MMC applications

FPGA-based implementation of sorting networks in MMC applica...

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European conference on Power Electronics and applications

作者： Mattia Ricco Laszlo Mathe Remus Teodorescu Aalborg University Aalborg Denmark

In this paper an implementation technique for field programmable Gate Array (FPGA) devices of two Sorting Networks (SNs) used for control of Modular Multilevel Converter (MMC) is presented. In such applications, the classical sorting algorithms are based on repetitive/recursive loops, and they are usually implemented in microcontrollers or DSPs. However, they are not convenient for hardware implementation due to their inherent sequential operation. Instead, the proposed SNs, are suitable for FPGA devices thanks to their fixed parallel structure that allows improving the timing performance of the capacitor voltage balancing algorithm. the advantages and the main challenges of the Bitonic SN and Even-Odd SN in MMC applications are discussed. Moreover, in order to pre-evaluate the required resources and the execution time, equations are derived for both the proposed SNs and then a comparison is performed between them. the proposed equations are validated by comparing the real required resources with the estimated ones by using the Xilinx Vivado Design Suite tool. Finally, the operation of the proposed Bitonic SN is also tested in Vivado Simulator, achieving the sorted list of 8 elements in 18 clock cycles as expected.

关键词： Sorting field programmable gate arrays Capacitors Voltage control logic gates Multiplexing Timing

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Reconfigurable circuit for implementation of family of 4-phase latch protocols

Reconfigurable circuit for implementation of family of 4-pha...

引用

international conference on field programmable logic and applications

作者： Jotham Vaddaboina Manoranjan Kenneth S. Stevens Department of Electrical and Computer Engineering University of Utah

this paper presents a novel reconfigurable circuit capable of implementing the entire family of 4-phase latch protocols. the architecture utilizes look-up-table based reconfigurable logic structures and fixed signal paths. the implemented circuit creates a fabric to realize a variety of high speed and low power controllers for asynchronous circuits on FPGAs. the circuit is implemented on the IBM Artisan 65nm node and its performance is compared with implementations on a Xilinx Virtex-5 chip that is manufactured on a similar node. A 4× improvement in speed and 3.3× improvement in energy per cycle is achieved.

关键词： Protocols field programmable gate arrays Table lookup Latches Routing Hazards Fabrics

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Towards an all-digital antenna array transmitter

Towards an all-digital antenna array transmitter

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international conference on field programmable logic and applications

作者： Daniel C. Dinis R. F. Cordeiro Arnaldo S. R. Oliveira José Vieira Departamento de Electrónica Universidade de Aveiro Campus Universitário de Santiago Aveiro Portugal

this PhD work presents a potential architecture and implementation for an FPGA-based all digital antenna array transmitter for wireless radio communications. By enabling the design of antenna arrays without external Digital-to-Analog Converters (DACs), external upconversion stages and without complex layouts, the analog front-end can be summed up to just amplification, filtering and radiation.

关键词： Antenna arrays Radio transmitters Transmitting antennas Modulation field programmable gate arrays Radio frequency

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