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检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

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Demonstration of a context-switch method for heterogeneous reconfigurable systems

Demonstration of a context-switch method for heterogeneous r...

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international conference on field programmable logic and applications

作者： Arief Wicaksana Alban Bourge Olivier Muller Frédéric Rousseau TIMA Laboratory - Grenoble-INP/UGA/CNRS Grenoble FRANCE

Nowadays, FPGAs are integrated in high-performance computing systems, servers, or even used as accelerators in System-on-Chip (SoC) platforms. Since the execution is performed in hardware, FPGA gives much higher performance and lower energy consumption compared to most microprocessor-based systems. However, the room to improve FPGA performance still exists, e.g. when it is used by multiple users. In multi-user approaches, FPGA resources are shared between several users. therefore, one must be able to interrupt a running circuit at any given time and continue the task at will. An image of the state of the running circuit (context) is saved during interruption and restored when the execution is continued. the ability to extract and restore the context is known as context-switch.

关键词： field programmable gate arrays Servers Context Interrupters Image restoration System-on-chip Hardware

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Overcoming resource underutilization in spatial CNN accelerators

Overcoming resource underutilization in spatial CNN accelera...

引用

international conference on field programmable logic and applications

作者： Yongming Shen Michael Ferdman Peter Milder Stony Brook University

Convolutional neural networks (CNNs) are revolutionizing a variety of machine learning tasks, but they present significant computational challenges. Recently, FPGA-based accelerators have been proposed to improve the speed and efficiency of CNNs. Current approaches construct an accelerator optimized to maximize the overall throughput of iteratively computing the CNN layers. However, this approach leads to dynamic resource underutilization because the same accelerator is used to compute CNN layers of radically varying dimensions. We present a new CNN accelerator design that improves the dynamic resource utilization. Using the same FPGA resources, we build multiple accelerators, each specialized for specific CNN layers. Our design achieves 1.3× higher throughput than the state of the art when evaluating the convolutional layers of the popular AlexNet CNN on a Xilinx Virtex-7 FPGA.

关键词： Digital signal processing field programmable gate arrays throughput Convolutional codes Image segmentation Dynamic scheduling Adders

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Modelling delay degradation due to NBTI in FPGA Look-up tables

Modelling delay degradation due to NBTI in FPGA Look-up tabl...

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international conference on field programmable logic and applications

作者： Mohammad Naouss François Marc University of Bordeaux IMS Laboratory Talence France

field-programmable Gate Arrays (FPGAs) benefit from the most advanced CMOS technology nodes, in order to meet the increasing demands of high performance and low power digital integrated circuits. this makes them susceptible to various reliability challenges at nano-scale. In this paper, we focus on aging degradation of the Look-up table (LUT) on FPGAs. We have characterized the delay degradation of LUT depending on the duty cycle of stress vectors. We have identified also that the duty cycle affects strongly the fall and moderately the rise delay of LUT due to the NBTI aging mechanism. Furthermore, a semi-empirical model of the degradation of LUT timing due to NBTI depending on the time and the duty cycle of stress vector has been investigated in this work. this model can be used to predict the degradation of a complex circuit implemented in a FPGA, and especially the risk of timing violations due to NBTI aging.

关键词： Delays Degradation Table lookup Stress field programmable gate arrays Aging Negative bias temperature instability

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Hardware acceleration of feature detection and description algorithms on low-power embedded platforms

Hardware acceleration of feature detection and description a...

引用

international conference on field programmable logic and applications

作者： Onur Ulusel Christopher Picardo Christopher B. Harris Sherief Reda R. Iris Bahar School of Engineering Brown University Providence RI

Image features are broadly used in embedded computer vision applications, from object detection and tracking to motion estimation and 3D reconstruction. Efficient feature extraction and description are crucial due to the real-time requirements of such applications over a constant stream of input data. High-speed computation typically comes at the cost of high power dissipation, yet embedded systems are often highly power constrained, making discovery of power-aware solutions especially critical for these systems. In this paper, we present a power and performance evaluation of three low cost feature detection and description algorithms implemented on various embedded systems (embedded CPUs, GPUs and FPGAs). We show that FPGAs in particular offer attractive solutions for both performance and power and describe several design techniques utilized to accelerate feature extraction and description algorithms on low-cost Zynq SoC FPGAs.

关键词： Feature extraction Algorithm design and analysis field programmable gate arrays Acceleration Detectors Hardware Power dissipation

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Designing a virtual runtime for FPGA accelerators in the cloud

Designing a virtual runtime for FPGA accelerators in the clo...

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international conference on field programmable logic and applications

作者： Mikhail Asiatici Nithin George Kizheppatt Vipin Suhaib A. Fahmy Paolo Ienne Ecole Poly technique Fédérale de Lausanne (EPFL) School of Computer and Communication Sciences Mahindra Ecole Centrale School of Engineering Sciences University of Warwick School of Engineering Email

FPGAs can provide high performance and energy efficiency to many applications; therefore, they are attractive computing platforms in a cloud environment. However, FPGA application development requires extensive hardware design knowledge which significantly limits the potential user base. Moreover, in a cloud setting, allocating a whole FPGA to a user is often wasteful and not cost effective due to low device utilization. To make FPGA application development easier, firstly, we propose a methodology that provides clean abstractions with high-level APIs and a simple execution model that supports both software and hardware execution. Secondly, to improve device utilization and share the FPGA among multiple users, we developed a lightweight runtime system that provides hardware-assisted memory virtualization and memory protection, enabling multiple applications to simultaneously execute on the device.

关键词： Cloud computing field programmable gate arrays Performance evaluation Manuals Computer architecture

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Connect on the fly: Enhancing and prototyping of cycle-reconfigurable modules

Connect on the fly: Enhancing and prototyping of cycle-recon...

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international conference on field programmable logic and applications

作者： Hao Zhou Xinyu Niu Junqi Yuan Lingli Wang Wayne Luk School of Microelectronics Fudan University China Dept. of Computing Imperial College London UK

this paper introduces cycle-reconfigurable modules that enhance FPGA architectures with efficient support for dynamic data accesses: data accesses with accessed data size and location known only at runtime. the proposed module adopts new reconfiguration strategies based on dynamic FIFOs, dynamic caches, and dynamic shared memories to significantly reduce configuration generation and routing complexity. We develop a prototype FPGA chip with the proposed cycle-reconfigurable module in the SMIC 130-nm technology. the integrated module takes less than the chip area of 39 CLBs, and reconfigures thousands of runtime connections in 1.2 ns. applications for large-scale sorting, sparse matrix-vector multiplication, and Memcached are developed. the proposed modules enable 1.4 and 11 times reduction in area-delay product compared with those applications mapped to previous architectures and conventional FPGAs.

关键词： Runtime Clocks field programmable gate arrays Customer relationship management Routing Hardware System-on-chip

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Low-latency TCP/IP stack for data center applications

Low-latency TCP/IP stack for data center applications

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international conference on field programmable logic and applications

作者： David Sidler Zsolt István Gustavo Alonso Systems Group ETH Zürich

TCP/IP is widely used both in the Internet as well as in data centers. the protocol makes very few assumptions about the underlying network and provides useful guarantees such as reliable transmission, in-order delivery, or control flow. the price for this functionality is complexity, latency, and computational overhead, which is especially pronounced in software implementations. While for Internet communication this is acceptable, the overhead is too high in data centers. In this paper, we explore how to optimize a TCP/IP stack running on an FPGA for data center applications with an emphasis on data processing (e.g., key value stores). Using a key-value store and a low-latency consensus protocol implemented on an FPGA as an example of the requirements that arise in data centers, we provide an extensive analysis of the overheads of TCP/IP and the solutions that can be adopted to minimize such an overhead. the proposed optimized TCP/IP stack minimizes tail latencies (a key metric in distributed data processing) and is efficiently implemented so as to be able to share the FPGA with application logic.

关键词： field programmable gate arrays TCPIP Memory management Bandwidth Payloads Engines Protocols

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Memory efficient and high performance key-value store on FPGA using Cuckoo hashing

Memory efficient and high performance key-value store on FPG...

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international conference on field programmable logic and applications

作者： Wei Liang Wenbo Yin Ping Kang Lingli Wang State Key Laboratory of ASIC and System Fudan University

Key-value stores (KVS) become critical in many applications because of the data explosion recently. there is a strong demand to improve the throughput and reduce the latency for KVS. FPGA-based parallel architecture can bring excellent performance and power efficiency. Cuckoo hashing has proven to be an efficient approach to implement KVS with good memory utilization and constant worst case access time. In this paper, an FPGA-based KVS implementation is proposed based on Cuckoo hashing, with a decoupled storage to achieve 81.7% memory utilization, and a pipeline scheme to achieve high performance. the latency of insert, search and delete operations is only 40 ns. And the throughput for search and delete can be 200 million requests per second (MRPS) which is 5× faster than [1]. Even when the load factor becomes 0.9, the throughput for insert can still achieve 147 MRPS.

关键词： Pipelines Arrays throughput field programmable gate arrays Memory management Clocks Random access memory

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Automated extra pipeline analysis of applications mapped to Xilinx UltraScale+ FPGAs

Automated extra pipeline analysis of applications mapped to ...

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international conference on field programmable logic and applications

作者： Ilya Ganusov Henri Fraisse Aaron Ng Rafael Trapani Possignolo Sabya Das Xilinx Inc. San Jose CA Dept. of Computer Engineering University of California Santa Cruz CA

this paper describes the methodology and algorithms behind extra pipeline analysis tools released in the Xilinx Vivado Design Suite version 2015.3. Extra pipelining is one of the most effective ways to improve performance of FPGA applications. Manual pipelining, however, often requires significant efforts from FPGA designers who need to explore various changes in the RTL and re-run the flow iteratively. the automatic pipelining approach described in this paper, in contrast, allows FPGA users to explore latency vs. performance trade-offs of their designs before investing time and effort into modifying RTL. We describe algorithms behind these tools which use simple cut heuristics to maximize performance improvement while minimizing additional latency and register overhead. To demonstrate the effectiveness of the proposed approach, we analyse a set of 93 commercial FPGA applications and IP blocks mapped to Xilinx UltraScale+ and UltraScale generations of FPGAs. the results show that extra pipelining can provide from 18% to 29% potential Fmax improvement on average. It also shows that the distribution of improvements is bimodal, with almost half of benchmark suite designs showing no improvement due to the presence of large loops. Finally, we demonstrate that highly-pipelined designs map well to UltraScale+ and UltraScale FPGA architectures. Our approach demonstrates 19% and 20% Fmax improvement potential for the UltraScale+ and UltraScale architectures respectively, with the majority of applications reaching their loop limit through pipelining.

关键词： Pipeline processing Registers field programmable gate arrays Pins Table lookup Algorithm design and analysis Pipelines

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Transparent FPGA flow

Transparent FPGA flow

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international conference on field programmable logic and applications

作者： Baptiste Delporte Anthony Convers Roberto Rigamonti Alberto Dassatti HES-SO — REDS Institute HEIG-VD — School of Business and Engineering Yverdon-les-Bains Switzerland

In this demo we propose an automated flow that allows the transparent execution of ordinary code on a heterogeneous platform including an FPGA. Our solution requires no change in the code, not even pragma indications to guide the optimization, and dynamically adapts its behaviour to the available data and the workload of the system. thus, the developer does not need to be aware of the target platform details, nor she has to forecast usage patterns to prevent performance bottlenecks, as the system transparently identifies parallelizable, computationally-intensive code fragments and dispatches them to a data flow overlay architecture built on top of the FPGA. Since the bitstream we use is fixed, and contrary to HLS, we can alter the functionalities offered by the FPGA on-the-fly to adapt them to current usage. Finally, since we operate at the LLVM's Intermediate Representation (IR) level, our approach is language-agnostic.

关键词： field programmable gate arrays Computer architecture Flow graphs Acceleration Performance evaluation Optimization Computers

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