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检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

共 1911 条记录，以下是641-650 订阅

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Exploring the use of shift register lookup tables for Keccak implementations on Xilinx FPGAs

Exploring the use of shift register lookup tables for Keccak...

引用

international conference on field programmable logic and applications

作者： Jori Winderickx Joan Daemen Nele Mentens KU Leuven ESAT/COSIC & iMinds Leuven Belgium STMicroelectronics Belgium Radboud University Nijmegen Netherlands

We explore the possibility of using shift register lookup tables (SRLs) for the implementation of Keccak on Xilinx FPGAs. the approach originates from the observation that the ρ step in combination with the state storage can be implemented as a collection of shift registers. this way, we achieve a slice-wise implementation using 25 shift registers of various lengths, resulting in 75 32-bit and 6 16-bit SRL primitives on a Virtex-5. this approach, however, does not comply efficiently with the common interface of Keccak. We therefore propose to utilize a modified interface in order to avoid the redundant storage of the state. this modified version of Keccak, with equivalent cryptographic strength, can be implemented without Block RAM, outperforming all previously proposed implementations in terms of the number of slices. Furthermore it outperforms several other lightweight slice-wise implementations in terms of throughput.

关键词： Shift registers Computer architecture field programmable gate arrays Clocks Random access memory throughput

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Improved resource sharing for FPGA DSP blocks

Improved resource sharing for FPGA DSP blocks

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international conference on field programmable logic and applications

作者： Bajaj Ronak Suhaib A. Fahmy School of Computer Science and Engineering Nanyang Technological University Singapore School of Engineering University of Warwick Coventry UK

Sharing multi-cycle hardware blocks like the DSP48E1 primitive in Xilinx FPGAs can result in significant resource savings, but complicates scheduling. For high-throughput, DSP blocks must be pipelined, which results in a high initiation interval (II) for resource shared implementations. In this paper, we propose a resource reduction technique that minimises DSP block usage while also offering improved II over traditional approaches. this is integrated in a high-level tool which takes datapath descriptions in C and generates synthesisable Verilog RTL with different levels of resource sharing. We demonstrate significantly improved throughput compared to traditional resource sharing while achieving resource reduction compared to resource unconstrained and HLS implementations. the approach explores an otherwise infeasible design space between resource unconstrained and traditional resource sharing methods.

关键词： Digital signal processing Resource management Schedules throughput Processor scheduling field programmable gate arrays Clocks

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GraVF: A vertex-centric distributed graph processing framework on FPGAs

GraVF: A vertex-centric distributed graph processing framewo...

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international conference on field programmable logic and applications

作者： Nina Engelhardt Hayden Kwok-Hay So Department of Electrical and Electronic Engineering The University of Hong Kong

FPGAs are promising platforms to efficiently execute distributed graph algorithms. Unfortunately, they are notoriously hard to program, especially when the problem size and system complexity increases. In this paper, we propose GraVF, a high-level design framework for distributed graph processing on FPGAs. It leverages the vertex-centric paradigm, which is naturally distributed and requires the user to define only very small kernels and their associated message semantics for the target application. the user design may subsequently be elaborated and compiled to the target system automatically by the framework. To demonstrate the flexibility and capabilities of the proposed framework, 4 graph algorithms with distinct requirements have been implemented, namely breadth-first search, PageRank, single source shortest path, and connected component. Results show that the proposed framework is capable of producing FPGA designs with performance comparable to similar custom designs while requiring only minimal input from the user.

关键词： Kernel field programmable gate arrays Computational modeling Programming Algorithm design and analysis Hardware Computer architecture

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Configurable and scalable belief propagation accelerator for computer vision

Configurable and scalable belief propagation accelerator for...

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international conference on field programmable logic and applications

作者： Jungwook Choi Rob A. Rutenbar IBM T. J. Watson Research Center Yorktown Heights NY

We demonstrate a novel FPGA-based accelerator architecture that can tackle a range of standard computer vision (CV) problems, with scalable performance and attractive speedups. the architecture relies on multiple pipelined processing elements (PEs) that can be configured to support various belief propagation (BP) settings for different CV tasks. Inside each PE, innovative implementation of Jump Flooding for efficient computation of BP solves the core configurability challenge. A novel block-parallel memory interface supports parallelization by distributing BP inference workloads across the PEs. Experimental results demonstrate that our accelerator achieves scalable performance with 11-41× speedup over standard sequential CPU implementations across a subset of well-known Middlebury and OpenGM benchmarks, with no compromise in quality of inference results. To the best of our knowledge, this is the first FPGA hardware implementation of BP capable of running a range of standard CV benchmarks with significant speedups.

关键词： field programmable gate arrays Hardware Computer architecture Bandwidth Computer vision Message passing Belief propagation

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JetStream: An open-source high-performance PCI Express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communication

JetStream: An open-source high-performance PCI Express 3 str...

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international conference on field programmable logic and applications

作者： Malte Vesper Dirk Koch Kizheppatt Vipin Suhaib A. Fahmy School of Computer Science University of Manchester Mahindra École Centrale School of Engineering University of Warwick

Many FPGA-based accelerators are constrained by the available resources and multi-FPGA solutions can be necessary for building more capable systems. Available PCIe solutions provide only FPGA-to-Host communication. In this paper we present JetStream, an open-source 1 modular PCIe 3 library, supporting not only fast FPGA-to-Host communication, but also allowing direct FPGA-to-FPGA communication which fully bypasses the memory subsystem. the direct mode saves memory bandwidth for multicast modes and permits to connect multiple FPGAs in various software defined topologies. We show the benefits of JetStream with a large FIR filter spanning four FPGA boards, achieving throughputs of up to 7.09 GB/s per link. Utilizing direct FPGA-to-FPGA transfers reduces the required memory bandwidth by up to 75%.

关键词： field programmable gate arrays Registers Bandwidth Payloads throughput Engines Hardware

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Bayesian inference implemented on FPGA with stochastic bitstreams for an autonomous robot

Bayesian inference implemented on FPGA with stochastic bitst...

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international conference on field programmable logic and applications

作者： Hugo Fernandes M. Awais Aslam Jorge Lobo João Filipe Ferreira Jorge Dias ISR - Institute of Systems and Robotics University of Coimbra Portugal ISR - Institute of Systems and Robotics DEEC University of Coimbra Portugal DEEC Portugal Khalifa University Abu Dhabi UAE

this paper presents an FPGA implementation of a machine performing exact Bayesian inference using stochastic bitstreams. We revisited stochastic computing, not to perform better computations with unreliable hardware, but to perform approximate computations with less hardware. the underlying trade-off is between precision and computation time. An automatic design of probabilistic machines that compute soft inferences with an arithmetic based on stochastic bitstreams is presented. the computation tree provided by a Bayesian inference software is used to define the stochastic circuit. Tests were performed and results presented concerning accuracy and resource usage of the stochastic computing implementation of Bayesian machines performing exact inference. An application example is given of a Bayesian sensorimotor system that performs obstacle avoidance for an autonomous robot, fully implemented on an FPGA. Some conclusions were drawn on the followed approach, providing insights for future implementations.

关键词： Bayes methods Stochastic processes Robots field programmable gate arrays Computational modeling Probabilistic logic Probability distribution

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Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC

Accelerating recurrent neural networks in analytics servers:...

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international conference on field programmable logic and applications

作者： Eriko Nurvitadhi Jaewoong Sim David Sheffield Asit Mishra Srivatsan Krishnan Debbie Marr Intel Corporation

Recurrent neural networks (RNNs) provide state-of-the-art accuracy for performing analytics on datasets with sequence (e.g., language model). this paper studied a state-of-the-art RNN variant, Gated Recurrent Unit (GRU). We first proposed memoization optimization to avoid 3 out of the 6 dense matrix vector multiplications (SGEMVs) that are the majority of the computation in GRU. then, we study the opportunities to accelerate the remaining SGEMVs using FPGAs, in comparison to 14-nm ASIC, GPU, and multi-core CPU. Results show that FPGA provides superior performance/Watt over CPU and GPU because FPGA's on-chip BRAMs, hard DSPs, and reconfigurable fabric allow for efficiently extracting fine-grained parallelisms from small/medium size matrices used by GRU. Moreover, newer FPGAs with more DSPs, on-chip BRAMs, and higher frequency have the potential to narrow the FPGA-ASIC efficiency gap.

关键词： field programmable gate arrays Recurrent neural networks Graphics processing units Random access memory logic gates Classification algorithms Runtime

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Modeling considerations for the hardware-software co-design of flexible modern wireless transceivers

Modeling considerations for the hardware-software co-design ...

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international conference on field programmable logic and applications

作者： Benjamin Drozdenko Matthew Zimmermann Tuan Dao Kaushik Chowdhury Miriam Leeser School of Electrical and Computer Engineering Northeastern University Boston Massachusetts

Software-defined radios have introduced new platforms for dynamically modifying wireless system designs, and heterogeneous computing has opened up implementing such designs on different computing elements. Our goal is to develop a hardware-software modeling environment that captures reusability of various processing blocks at the physical layer for several modern protocols, and makes decisions regarding whether each processing block should be part of reconfigurable hardware or embedded processor software based on timing constraints and power budgets for the overlying applications. Our approach creates several different MathWorks Simulink model variants for both the transmitter and the receiver, each with a different boundary between hardware and software components. Using the 802.11a standard as an example, we use these models to generate a bitstream for the FPGA and executable code for the ARM processor on a Xilinx Zynq system-on-chip. Our results collect such metrics as data path delay, resource utilization, and power usage and demonstrate how to enhance the SDR design.

关键词： field programmable gate arrays Wireless communication Data models Hardware Software packages Delays

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Measure twice and cut once: Robust dynamic voltage scaling for FPGAs

Measure twice and cut once: Robust dynamic voltage scaling f...

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international conference on field programmable logic and applications

作者： Ibrahim Ahmed Shuze Zhao Olivier Trescases Vaughn Betz Department of Electrical and Computer Engineering University of Toronto Toronto ON Canada

Although dynamic voltage scaling (DVS) is a popular power reduction solution that has been widely used by processors and ASICs, it is still not commercially adopted by FPGAs. A unique feature of FPGAs that leads to challenges in adopting DVS is that the critical path and hence the minimum safe V dd depends on the configured application. We present a robust DVS technique that solves these challenges. For each application, we generate a calibration table (CT) that stores the actual failing points of that application on a specific FPGA, under various operating conditions. this CT is used to scale V dd while the application is running to guarantee safe operation with minimal power consumption. We develop an automated tool (FRoC) that ensures a Fast-Robust-Calibration of the FPGA to any application using it. FRoC ensures that the calibration process is invisible to FPGA users and does not add any extra manual steps to the design process. We show that our proposed DVS technique achieves a 33% total power reduction on two large applications.

关键词： field programmable gate arrays Voltage control Calibration Delays Testing Registers Temperature measurement

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Optimising Sparse Matrix Vector multiplication for large scale FEM problems on FPGA

Optimising Sparse Matrix Vector multiplication for large sca...

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international conference on field programmable logic and applications

作者： Paul Grigoraş Pavel Burovskiy Wayne Luk Spencer Sherwin Department of Computing Imperial College London Department of Aeronautics Imperial College London

Sparse Matrix Vector multiplication (SpMV) is an important kernel in many scientific applications. In this work we propose an architecture and an automated customisation method to detect and optimise the architecture for block diagonal sparse matrices. We evaluate the proposed approach in the context of the spectral/hp Finite Element Method, using the local matrix assembly approach. this problem leads to a large sparse system of linear equations with block diagonal matrix which is typically solved using an iterative method such as the Preconditioned Conjugate Gradient. the efficiency of the proposed architecture combined with the effectiveness of the proposed customisation method reduces BRAM resource utilisation by as much as 10 times, while achieving identical throughput with existing state of the art designs and requiring minimal development effort from the end user. In the context of the Finite Element Method, our approach enables the solution of larger problems than previously possible, enabling the applicability of FPGAs to more interesting HPC problems.

关键词： Sparse matrices field programmable gate arrays Computer architecture Finite element analysis Kernel Iterative methods Space exploration

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