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检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

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Time-borrowing platform in the Xilinx UltraScale+ family of FPGAs and MPSoCs

Time-borrowing platform in the Xilinx UltraScale+ family of ...

引用

international conference on field programmable logic and applications

作者： Ilya Ganusov Benjamin Devlin Xilinx Inc. San Jose CA

this paper presents enhancements to the Xilinx UltraScale+ clocking architecture to support fine-grain time-borrowing. Time borrowing improves performance by redistributing timing slack between fast and slow paths. the Ultra-Scale+ architecture introduces programmable hardware delays and pulse generators embedded in the clocking tree to support time-borrowing based both on clock skew scheduling and pulsed latches. this programmable hardware allows borrowing from a few picoseconds to multiple nanoseconds between sequential pipeline stages without any changes to RTL, placement or routing. Vivado algorithms automatically determine when to skew flip-flop clock or convert them to pulsed latches to achieve the highest possible performance. Using the default Vivado flow, this programmable time-borrowing platform delivers 5.5% F max increase on average over a suite of 89 industrial designs. It is especially effective on high-speed applications, delivering up to 13.7% F max increase on individual designs. We also demonstrate that using non-default features, such as delays cascades or increasing hold margin, can increase average performance gains to 7.4% and 8.5%, respectively. this platform incurs minimum area (less than 0.1% of total chip area) while staying robust in the presence of tight hold constraints and increasing process variation.

关键词： Clocks Latches Delays Pipelines field programmable gate arrays Routing

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Dimensionality reduction of hyperspectral images using reconfigurable hardware

Dimensionality reduction of hyperspectral images using recon...

引用

international conference on field programmable logic and applications

作者： Daniel Fenzández Carlos González Daniel Mozos Department of Computer Architecture and Automatics Complutense University of Madrid Madrid Spain

Remotely sensed hyperspectral imaging is a very active research area, with numerous contributions in the recent scientific literature. To carry out these investigations, it is necessary to collect large amounts of information that will be processed on satellite or airborne platforms using parallel processing techniques on multi core systems or Graphics Processing Units, trying to avoid excessive energy consumption. Due to the high dimensionality of the data, algorithms analyzing hyperspectral images have a high computational cost. this cost is a significant disadvantage in applications that require real-time response, such as fire tracing, prevention and monitoring of natural disasters, chemical spills and other environmental pollution, etc. To solve these problems, one of the solutions most used is the dimensional reduction, which removes noise and redundant information of images. therefore, it is possible to reduce significantly the size of the images, and improve the complexity of the algorithms and data storage. Moreover, field-programmable Gate Arrays are specially recommended in remotely sensed applications that require real-time response due to their features such as reconfiguration, low consumption, compact size and high computing power on board. In this work, we propose the implementation in reconfigurable hardware of the principal component analysis (PCA) algorithm to carry out the dimensional reduction of hyperspectral images. Experimental results demonstrate that our hardware version of the PCA algorithm exhibits real-time performance.

关键词： Principal component analysis Hyperspectral imaging field programmable gate arrays Covariance matrices Hardware Real-time systems

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EURECA compilation: Automatic optimisation of cycle-reconfigurable circuits

EURECA compilation: Automatic optimisation of cycle-reconfig...

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international conference on field programmable logic and applications

作者： Xinyu Niu Nicholas Ng Tomofumi Yuki Shaojun Wang Nobuko Yoshida Wayne Luk Dept. of Computing Imperial College London UK

EURECA architectures have been proposed as an enhancement to existing FPGAs, to enable cycle-by-cycle reconfiguration. applications with irregular data accesses, which previously cannot be efficiently supported in hardware, can be efficiently mapped into EURECA architectures. One major challenge to apply the EURECA architectures to practical applications is the intensive design efforts required to analyse and optimise cycle-reconfigurable operations, in order to obtain accurate and high-performance results while underlying circuits reconfigure cycle by cycle. this work proposes novel compiler support for EURECA-based designs. the compiler adopts (a) techniques based on session types to automatically derive a runtime reconfiguration scheduler that guarantees design correctness, and (b) a streaming circuit model to ensure high-performance circuits. three benchmark applications -large-scale sorting, Memcached, and Sparse Matrix Vector Multiplication (SpMV)- developed with the proposed compiler support show up to 11.2 times (21.8 times when architecture scales) reduction in area-delay product when compared with conventional architectures, and achieve up to 39% improvements compared with manually optimised EURECA designs.

关键词： Ports (Computers) Runtime Computer architecture Protocols Clocks field programmable gate arrays Kernel

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FMER: A hybrid configuration memory error recovery scheme for highly reliable FPGA SoCs

FMER: A hybrid configuration memory error recovery scheme fo...

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international conference on field programmable logic and applications

作者： Dimitris Agiakatsikas Ediz Cetin Oliver Diessel School of Computer Science and Engineering UNSW Australia School of Electrical Engineering and Telecommunications UNSW Australia

High-reliability SRAM-based field programmable Gate Array (FPGA) designs that are deployed in space are commonly triplicated to mask Single Event Upsets (SEUs) and employ either scrubbing or modular reconfiguration to recover from radiation-induced configuration memory errors. Scrubbing benefits from vendor support and clears errors anywhere in the design but suffers from longer recovery times and higher energy use. Module-based error recovery is more energy efficient and responsive but repairs only corrupted TMR modules, leaving the supporting parts of the design such as pins or routing that are not included in the modules unrecovered. this paper proposes and assesses a hybrid technique we refer to as Frame- and Module-based Error Recovery (FMER) that uses modular reconfiguration to repair faulty TMR modules and otherwise scrubs the supporting parts of the design. We derive and compare the reliability, availability and power consumption of TMR-based System on Chip (SoC) designs that incorporate FMER, modular reconfiguration alone, blind scrubbing and no recovery. Our results reveal that FMER has the highest reliability and availability of the studied techniques in high radiation environments or when a mission's energy budget is limited.

关键词： Tunneling magnetoresistance Reliability Energy consumption Pins field programmable gate arrays Maintenance engineering Markov processes

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DT-CGRA: Dual-track coarse-grained reconfigurable architecture for stream applications

DT-CGRA: Dual-track coarse-grained reconfigurable architectu...

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international conference on field programmable logic and applications

作者： Xitian Fan Huimin Li Wei Cao Lingli Wang State Key Laboratory of ASIC and System Fudan University Shanghai China

this paper presents a new type of coarse-grained reconfigurable architecture (CGRA) for the object inference domain in machine learning. the proposed CGRA is optimized for stream processing and a correspondent programming model called dual-track model is proposed. the CGRA is realized in Verilog HDL and implemented in SMIC 55 nm process, with the footprint of 3.79 mm 2 and consuming 1.79 W at 500 MHz. To evaluate the performance, eight machine-learning algorithms including HOG, CNN, k-means, PCA, SPM, linear-SVM, Softmax and Joint-Bayesian are selected as benchmarks. these algorithms cover a general machine learning flow in object inference domain: feature extraction, feature selection and inference. the experimental results show that the proposed CGRA can gain 1443× average energy efficiency comparing to the Intel i7-3770 CPU and 7.82× energy efficiency comparing to a high performance FPGA solution [19].

关键词： Kernel Programming Reconfigurable architectures Energy efficiency Context Arrays

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Effects of I/O routing through column interfaces in embedded FPGA fabrics

Effects of I/O routing through column interfaces in embedded...

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international conference on field programmable logic and applications

作者： Christophe Huriaux Olivier Sentieys Russell Tessier Inria IRISA Lannion France Department of Electrical and Computer Engineering University of Massachusetts Amherst MA

the emergence of 2.5D and 3D packaging technologies enables the integration of FPGA dice into more complex systems. Both heterogeneous manycore designs, which include an FPGA layer, and interposer-based multi-FPGA systems support the inclusion of reconfigurable hardware in 3D-stacked integrated circuits. In these architectures, the communication between FPGA dice or between FPGA and fixed-function layers often takes place through dedicated communication interfaces spread over the FPGA logic fabric, as opposed to an I/O ring around the fabric. In this paper, we investigate the effect of organizing FPGA fabric I/O into coarse-grained interface blocks distributed throughout the FPGA fabric. Specifically, we consider the quality of results for the placement and routing phases of the FPGA physical design flow. We evaluate the routing of I/O signals of large applications through dedicated interface blocks at various granularities in the logic fabric, and study its implications on the critical path delay of routed designs. We show that the impact of such I/O routing is limited and can improve chip routability and circuit delay in many cases.

关键词： field programmable gate arrays Fabrics Computer architecture Routing three-dimensional displays through-silicon vias Video recording

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High-level synthesis for medical image processing on Systems on Chip: A case study

High-level synthesis for medical image processing on Systems...

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international conference on field programmable logic and applications

作者： Fraser D Robinson Louise H Crockett William H Nailon Robert W Stewart Department of Biomedical Engineering University of Strathclyde Glasgow UK Department of Electronic and Electrical Engineering University of Strathclyde Glasgow UK Department of Oncology Physics Edinburgh Cancer Centre Edinburgh UK

Adaptive radiotherapy is a technique intended to increase the accuracy of radiotherapy. Currently, it is not clinically feasible due to the time required to process the images of patient anatomy. Hardware acceleration of image processing algorithms may allow them to be carried out in a clinically acceptable timeframe. this paper presents the experiences encountered using high-level synthesis tools to design an accelerated segmentation algorithm for computed tomography images targeted for implementation on a System on Chip. Hardware coprocessors and their interfaces for optimal threshold generation and 3D mean filter algorithms were synthesised from C++ functions. Hardware acceleration significantly outperformed the software only implementation. the high-level synthesis tools allowed the rapid exploration of different design options. However, hardware design knowledge was still necessary in order to interpret the results effectively.

关键词： Hardware Algorithm design and analysis Acceleration Software algorithms Software Coprocessors field programmable gate arrays

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Fast and robust hashing for database operators

Fast and robust hashing for database operators

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international conference on field programmable logic and applications

作者： Kaan Kara Gustavo Alonso Dept. of Computer Science ETH Zurich Switzerland

Hashing is an essential part of many database operators, such as joins or aggregation, especially when executed in parallel. Often, database engines resort to using easily computed hash functions like modulo to prevent that hashing becomes a bottleneck. the disadvantage of simple hash functions is that they produce imperfect data distributions, particularly when the data is skewed. Robust hash functions produce balanced distributions but they are computationally expensive. Our purpose in this paper is to break the present trade-off between robustness and performance. We achieve this by showing how to implement robust hash functions suitable for database operators on an FPGA. Our target platform (Intel QuickAssist QPI-FPGA) provides a shared memory architecture between the CPU and the FPGA, enabling database engines to use the hardware hashing without any modifications to their memory layout. Depending on the hash function, we achieve 6.6× improvement over pure software implementations. We also show how to integrate hardware hashing in a hybrid hash table without any acceleration overhead.

关键词： field programmable gate arrays Hardware Software Robustness Databases Acceleration Computer architecture

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TeSHoP: A Temperature Sensing based Hotspot-Driven Placement technique for FPGAs

TeSHoP: A Temperature Sensing based Hotspot-Driven Placement...

引用

international conference on field programmable logic and applications

作者： Weina Lu Yu Hu Jing Ye Xiaowei Li Graduate University of Chinese Academy of Sciences Chinese Academy of Sciences Institute of Computing Technology

the rapid shrinking of the feature size in CMOS technology has significantly increased the power density of integrated circuits, leading to excessive temperature. though online thermal management techniques such as DVFS and task migration can mitigate the temperature issue, but usually incur significant performance penalty. therefore, it is crucial to optimize temperature at the design stage. In this work, we propose the TeSHoP, a Temperature Sensing based Hotspot-Driven Placement technique for FPGAs. Firstly, the un-optimized circuit along with a sensor network is run in FPGA to obtain the real temperature profile of the circuit. then, based on the temperature profile, we proceed a one-off adjustment of the circuit placement for hotspot optimization. the optimization is modeled as a Hyper Minimum Bipartite Matching problem for solving. We implement the whole optimization flow in a real FPGA, with extension of the VTR-to-Bitstream tool. Experimental results on Xilinx Virtex-6 FPGA show that the reduction of peak temperature and the improvement of thermal uniformity can be up to 7.5°C and 13.9% respectively.

关键词： Temperature sensors field programmable gate arrays Optimization Temperature measurement Benchmark testing Routing

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Trojans modifying soft-processor instruction sequences embedded in FPGA bitstreams

Trojans modifying soft-processor instruction sequences embed...

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international conference on field programmable logic and applications

作者： Ismail San Nicole Fern Cetin Kaya Koc Kwang-Ting Cheng University of California Santa Barbara CA USA Anadolu University Eskisehir Turkey

Reconfigurable platforms such as FPGAs and CPLDs are used to implement flexible and lightweight embedded systems often using soft-processors and a fixed instruction sequence stored in block memories. the bitstream format is proprietary for most vendors, however, in this work we demonstrate how to identify and extract block memory contents within the bitstream, allowing an adversary to learn and possibly modify the fixed instruction sequence. Manipulating the instruction sequence by inserting a Trojan in the bitstream as opposed to in the RTL code allows an adversary to bypass many verification steps. Moreover, the proposed Trojans only add extra instructions to the sequence to leak secret information, and do not change the original program behavior, making them virtually impossible to detect using functional tests. We present a case study where a Trojan is injected into a MIPS AES encryption program to leak internal state information by adding extra instructions from the available ones without changing the original program behavior.

关键词： field programmable gate arrays Decoding Trojan horses Encryption Embedded systems Algorithm design and analysis

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