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检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

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the speed of diversity: Exploring complex FPGA routing topologies for the global metal layer

The speed of diversity: Exploring complex FPGA routing topol...

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international conference on field programmable logic and applications

作者： Oleg Petelin Vaughn Betz Department of Electrical and Computer Engineering University of Toronto Toronto Canada

the rapid growth of wire RC delay with technology scaling has put increasing pressure on FPGA architects to make more efficient use of the different layers available in the metal stack. While commercial FPGA architectures have implemented the majority of inter-logic-block wiring on the lower metal layers and a small fraction of wires on the least-resistive upper metal layers, published explorations have largely ignored the question of how to exploit the different layers of the metal stack, focusing instead on very simple interconnect topologies and physical models. We generate VPR architectures and detailed area and delay models at the 22nm node and present enhancements to VPR that enable us to describe and evaluate complex interconnect topologies. We use our new architectures and tool enhancements to explore complex interconnect patterns suitable for modern unidirectional architectures and suggest topologies to connect wires on the semi-global and global metal layers. the proposed topologies improve the critical path routing delay by 17% compared to architectures with no global layer wires, and by 5-13% compared to architectures with global layer wires using the default VPR switch pattern.

关键词： Wires Metals Routing Switches field programmable gate arrays Delays Computer architecture

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Search-based synthesis of approximate circuits implemented into FPGAs

Search-based synthesis of approximate circuits implemented i...

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international conference on field programmable logic and applications

作者： Zdenek Vasicek Lukas Sekanina Faculty of Information Technology IT4Innovations Centre of Excellence Brno Czech Republic

Approximate computing is capable of exploiting the error resilience of various applications with the aim of improving their parameters such as performance, energy consumption and area on a chip. In this paper, a new systematic approach for the approximation and optimization of circuits intended for LUT-based field programmable gate arrays (FPGAs) is proposed. In order to deliver a good trade-off between the quality of processing and implementation cost, the method employs a genetic programming-based optimization engine. the circuits are internally represented and optimized at the gate level. the resulting LUT-based netlists are obtained using a commercial FPGA tool. In the experimental part, four commonly available commercial FPGA design tools (Xilinx ISE, Xilinx Vivado, Precision, and Quartus) and state-of-the-art academia circuit synthesis and optimization tool ABC are compared. the quality of approximated circuits is evaluated using relaxed equivalence checking by means of Binary decision diagrams. An important conclusion is that the improvements (i.e. area reductions) at the gate level are preserved by the FPGA design tools and thus the number of LUTs is also adequately reduced. It was shown that the current state-of-the-art synthesis tools provide (for some instances) the results that are far from an optimum. For example, a 40% reduction (68 LUTs) was achieved for `clmb' benchmark circuit (Bus Interface) without introducing any error. Additional 43% reduction can be obtained by introducing only a 0.1% error.

关键词： logic gates field programmable gate arrays Table lookup Optimization Boolean functions Design tools

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SoCLog: A real-time, automatically generated logging and profiling mechanism for FPGA-based Systems On Chip

SoCLog: A real-time, automatically generated logging and pro...

引用

international conference on field programmable logic and applications

作者： Ioannis Parnassos Panagiotis Skrimponis Georgios Zindros Nikolaos Bellas Center for Research & Technology Hellas (CERTH) University of Thessaly Greece

Recent advances in FPGA technology and the proliferation of High Level Synthesis (HLS) tools makes it possible to implement complex System on Chip (SoC) designs that realize complete applications in a single FPGA device. To be able to exploit the large performance vs. area search space of such modern FPGA-based SoCs, system architects must have the appropriate performance analysis tools to evaluate-preferably at runtime-the computational requirements and the data flow of such a system to determine potential performance bottlenecks when running realistic workloads. In this paper we introduce SoCLog, a framework that automatically enhances the platform architecture with additional hardware components used to generate activity logs when the base SoC architecture executes an application. this real-time information can be analyzed by the system designer to expose performance bottlenecks not only on aggregate, but also at clock cycle granularity thus revealing potential design inefficiencies when there is burst of activity in the system. We evaluate our framework with a number of SoC designs to show that such a logging information can be valuable for the design of a complex SoC in a modern FPGA with minimal area overhead.

关键词： Hardware field programmable gate arrays Discrete cosine transforms Computer architecture Kernel Benchmark testing

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Optimal random sampling based path planning on FPGAs

Optimal random sampling based path planning on FPGAs

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international conference on field programmable logic and applications

作者： Size Xiao Adam Postula Neil Bergmann School of Information Technology and Electrical Engineering The University of Queensland Australia

Random sampling based path planning algorithms have shown their high efficiency in robotics, navigation and related fields. the Rapidly-Exploring Random Trees (RRT) is the typical method and works well in a variety of applications. Due to the sub-optimal issue of original RRT, the recent algorithm, known as RRT*, significantly improves the optimality of solution by adding the “cost review” procedure. However, the original RRT experiences the bottle neck of complicated iterations and it becomes worse in RRT*. this paper presents the developed hardware architecture for RRT*, which fully exploits the parallel potential of algorithm. Unlike the sequential execution in software, the “exploration” and “review” are identified as independent processes and executed in parallel. For the complicated operation of inserting vertexes, one pipelined Kd-tree constructor is designed to fast rebuild the tree when new vertex generated. Furthermore, to speed up the near neighbors and nearest neighbor searching, the vertexes are stored in separate Kd-trees so that the search processes can be carried out concurrently in each data tree. this work explores the possible and power-efficient RRT* hardware architecture on FPGAs compared to PC implementation.

关键词： Algorithm design and analysis Hardware Computer architecture Acceleration Sorting Path planning field programmable gate arrays

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HeteroSim: A heterogeneous CPU-FPGA simulator

HeteroSim: A heterogeneous CPU-FPGA simulator

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international conference on field programmable logic and applications

作者： Liang Feng Hao Liang Sharad Sinha Wei Zhang Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Clearwater Bay Kowloon Hong Kong

Heterogeneous computing is rapidly gaining increased attention due to the promise it holds in overcoming power and performance walls in traditional computing systems. With its focus on customized processing nodes dedicated to the different tasks in an application, it is hoped that these walls will be overcome. therefore, CPU-FPGA co-architectures are also gaining ground in application areas like recognition, mining, search, datacenter etc. However, research in CPU-FPGA co-architecture is constrained by the available synthesis and simulation tools which do not provide an integrated system level simulation and architectural exploration environment. this becomes critical when we incorporate novel memory hierarchies, multi-processor chip architectures, hardware level cache coherence etc. In this paper, we describe our open source and integrated system level simulator and architecture exploration tool called HeteroSim. It supports x86 based multi-core processor combined with a FPGA via bus-based architecture. It allows integrated system level simulation and returns performance metrics to understand application performance with respect to the simulated architectural configuration.

关键词： Computer architecture field programmable gate arrays Kernel Acceleration Data models Hardware Program processors

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Model-based optimization of High Level Synthesis directives

Model-based optimization of High Level Synthesis directives

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international conference on field programmable logic and applications

作者： Charles Lo Paul Chow Department of Electrical and Computer Engineering University of Toronto Toronto Ontario Canada

High Level Synthesis (HLS) tools improve the speed of FPGA hardware design entry compared to traditional hardware description languages by raising the level of design abstraction. Using compiler directives to guide the tool, a wide variety of hardware architectures can be obtained without modification of the original behavioural code. However, selecting an optimal application of directives from this large design space can be daunting and time-consuming for a designer since evaluating a particular setting of directives requires running the FPGA tool flow. this work considers the use of sequential model-based optimization (SMBO) methods for automatically selecting directive settings. these methods construct models of the design space to guide the optimization process and minimize the number of tool evaluations. In this paper, we evaluate the use of SMBO for selecting HLS directives and extend the method to relate multiple uses of the same directive within a design. We observe that SMBO can quickly find optimal directive settings in a space of tens of thousands of possible directive configurations and find that our proposed extension can further improve the convergence rate over the standard method.

关键词： Optimization Hardware Gaussian processes field programmable gate arrays Context High level synthesis Standards

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Approximate Frequent Itemset Mining for streaming data on FPGA

Approximate Frequent Itemset Mining for streaming data on FP...

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international conference on field programmable logic and applications

作者： Yubin Li Yuliang Sun Guohao Dai Qiang Xu Yu Wang Huazhong Yang Dept. E.E. Tsinghua University Beijing China Dept. C.S. Chinese University of Hong Kong Hong Kong China

Frequent Itemset Mining (FIM) is designed to find frequently occurring itemsets among a series of transactions. It is extremely memory and time expensive. Frequent Itemset Mining from a Data Stream (FIM-DS) is even more challenging since storing the infinite data to memory is infeasible. In recent years, researchers have proposed various approximation algorithms for FIM-DS. However, the computation complexity is still high, and these methods are difficult to be accelerated using hardware accelerators. In this paper, we propose a Space-Saving based approximate algorithm for FIM-DS. It avoids exponential candidates generation and comparisons. We realize a hardware accelerator design and implement it on an FPGA platform. Experimental results show that our algorithm in software implementation achieves up to 8.4× speedup for transactions with small item database, and our hardware accelerator achieves up to 50,000× speedup for transactions with small number of items, and 5.3× speedup for transactions with extremely large number of items.

关键词： Itemsets field programmable gate arrays Pipelines Acceleration Table lookup

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An implementation method of the box filter on FPGA

An implementation method of the box filter on FPGA

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international conference on field programmable logic and applications

作者： Sichao Wang Tsutomu Maruyama Systems and Information Engineering University of Tsukuba Tsukuba Ibaraki Japan

the box filter is widely used in image processing. Its computational complexity is low, and many other filters can be realized by using different size box filters. the implementation method of the box filter that is widely used in the software programs requires an array to store data, the size of which is filter size × image width. this array often limits the feasibility of the box filter on FPGA, because its size is proportional to the image width. In this paper, we show an implementation method of the box filter that requires less memory. Two types of wide-width but shallow memory are required in this method, but these memory can be efficiently realized on FPGA using distributed RAMs and block RAMs. In this method, the image is scanned in zigzag. the performance is decreased because of the necessity to overlap the zigzag scan, but it is fast enough for practical use. this zigzag scan enable to reduce the memory size to store data, but extra line buffers are required. Our approach is specially effective for applications that calculate cross-correlations for finding the best matching, because the overhead caused by the extra line buffers becomes relatively small in these applications. We show the effectiveness of our method using a stereo vision program based on the cost aggregation with guided filter.

关键词： Random access memory Barium field programmable gate arrays Memory management Stereo vision System-on-chip Mathematical model

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conference Digest - 24th international conference on field programmable logic and applications, FPL 2014

Conference Digest - 24th International Conference on Field P...

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24th international conference on field programmable logic and applications, FPL 2014

ISBN: (纸本)9783000446450

the proceedings contain 130 papers. the topics discussed include: FPGA implementation of low-power split-radix FFT processors;a combination of multi-edge coding and independent coding lines for time-to-digital conversion;using high-level knowledge to enhance data channels in FPGA streaming systems;hardware conversion of neural networks simulation models for neural processing accelerator implemented as FPGA-based SoC;efficient multi-standard cognitive radios on FPGAs;biomedical image processing and reconstruction with dataflow computing on FPGAs;improve defect tolerance in a cluster of a SRAM-based mesh of cluster FPGA using hardware redundancy;efficient implementation of a single-precision floating-point arithmetic unit on FPGA;a fast and scalable FPGA damage diagnostic service for R3TOS using BIST cloning technique;a soft-core processor for finite field arithmetic with a variable word size accelerator;and ultrasmall: the smallest MIPS soft processor.

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Artificial Intelligence Research and Development : Proceedings of the 19th international conference of the Catalan Association for Artificial Intelligence, Barcelona, Catalonia, Spain, October 19-21, 2016

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丛书名： Frontiers in Artificial Intelligence and applications, volume 288

2016年

作者： Nebot, A. Binefa, X. López de Mántaras, Ramon

ISBN: (纸本)9781614996958;9781614996965

the Catalan Association for Artificial Intelligence (ACIA) was formed in 1994 with the aim of promoting cooperation between researchers in artificial intelligence within the Catalan speaking community. this objective has been achieved and widened since the association held their first conference in 1998, and the annual conference of the association has become an international event presenting and discussing the latest research in AI, which attracts AI researchers from around the world. this book presents the proceedings of the 19th international conference of the Catalan Association for Artificial Intelligence (CCIA 2016), held in Barcelona, Spain, on 19-21 October. From a total of 50 original contributions, 16 long papers and 22 short papers were accepted for presentation at the conference on the basis of their relevance, originality and technical validity. the book is divided into 7 sections: Invited Talks (synopsis only); Vision and Robotics; logic, Constraint Satisfaction and Qualitative theory; Classification and Clustering; Modelling; Planning and Recommender Systems; Lexical Knowledge Representation and Natural Language Processing. Providing an overview of the latest developments in the field, this book will be of interest to all those whose work involves research into, and the application of, artificial intelligence.

关键词： Artificial intelligence--Congresses

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