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Efficient processing of phased array radar in sense and avoid application using heterogeneous computing

Efficient processing of phased array radar in sense and avoi...

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international conference on field programmable logic and applications

作者： Luke Newmeyer Doran Wilde Brent Nelson Michael Wirthlin Department of Electrical and Computer Engineering Brigham Young University Provo Utah U.S.A.

this paper describes a tightly integrated phased-array radar platform for a UAV-based sense and avoid application. the system leverages heterogeneous computing on a Zynq 7000 SoC processor to efficiently process the large streams of radar data required to guide a small Unmanned Air Vehicle (UAV) away from obstacles and intruding air vehicles. the system is mounted on a small UAV which requires stringent size, weight, and power constraints, and thus data processing must be done efficiently. the system is implemented on the commercial MicroZed development board. Low-level radar data-stream processing is performed in the FPGA fabric on the Zynq, which accelerates processing and improves energy efficiency. the Zynq ARM CPUs are used to perform higher-level radar processing and avoidance algorithms. the final proof of concept system is 2.25 × 4 × 1.5 in 3 weighing only 120 g (0.26 lbs) and consumes 8 watts of power. As an example, the improvements demonstrated by executing the FFT algorithm in hardware will be highlighted where hardware FFT processing provides a 17× improvement in processing time and a 49× improvement in energy efficiency over a CPU only implementation on the same SoC.

关键词： Hardware field programmable gate arrays Unmanned aerial vehicles Phased arrays Radar applications Collision avoidance

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Improving the efficiency of PUF-based key generation in FPGAs using variation-aware placement

Improving the efficiency of PUF-based key generation in FPGA...

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international conference on field programmable logic and applications

作者： Shrikant Vyas Naveen Kumar Dumpala Russell Tessier Daniel E. Holcomb Department of Electrical and Computer Engineering University of Massachusetts Amherst

Reconfigurable systems often require secret keys to encrypt and decrypt data. applications requiring high security commonly generate keys based on physical unclonable functions (PUFs), circuits which use random manufacturing variations to produce secret keys that are unique to each device. the security of PUF-based keys comes at a high hardware cost. Due to the need for error correction to extract reliable keys from noisy PUFs, the total cost of an n-bit key far exceeds just the cost of producing n bits of PUF output. In this work, we propose variation-aware intra-FPGA PUF placement to reduce the area cost of PUF-based keys on FPGAs. We show that placing PUF instances according to the random variations of each chip instance reduces the bit error rate of the PUFs and consequently greatly reduces the overall cost of key generation. the proposed variation-aware placement approach is applicable to any PUF-based system implemented in reconfigurable logic. We demonstrate our approach on a Xilinx Zynq-7000 programmable SoC using FPGA-specific PUFs with code-offset error correction based on BCH codes. We quantify the effectiveness of our approach by comparing the implementation costs of the same system when using the default approach of variation-agnostic placement and our proposed variation-aware placement. It is shown that our approach reduces the area required for PUF and error-correction circuitry by about 50% while achieving equivalent reliability.

关键词： field programmable gate arrays Reliability Bit error rate Error correction codes Cryptography Error correction

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Harnessing programmable SoCs to develop cost-effective network quality monitoring devices

Harnessing Programmable SoCs to develop cost-effective netwo...

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international conference on field programmable logic and applications

作者： M. Ruiz J. Ramos G. Sutter S. López-Buedo J.E. López de Vergara C. Sisterna High-Performance Computing and Networking Research Group Universidad Autónoma de Madrid Spain NAUDIT HPCN Spain Instituto de Investigaciones Antisísmicas Universidad Nacional de San Juan Argentina

Networks are currently essential for computing: It is therefore essential to guarantee the quality of network links in order to ensure a proper operation of computing systems. However, a widespread deployment of network monitoring devices might not be economically feasible. In this paper, we propose the use of programmable System-on-Chip FPGAs (PSoCs) for enabling a comprehensive testing of networks. Software-only solutions are no longer valid, because the timescales of current networks call for custom-hardware solutions. thus, we show that PSoCs are a perfect fit for network quality monitoring devices, by mapping the required measurements to the capabilities of such devices. In order to demonstrate the benefits of PSoCs to monitor the quality of network links, we have developed a prototype based on Xilinx Zynq that is capable of measuring the key performance indicators of Gigabit Ethernet networks, namely: available bandwidth, packet loss, delay and jitter. the monitoring probe features GPS-based timestamping, thus enabling the construction of network delay maps. We present the benefits of the proposed approach in terms of cost and simplicity, and we also show how it could be expanded to multi-Gb/s networks.

关键词： Monitoring Clocks Synchronization Delays field programmable gate arrays Global Positioning System Receivers

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Runtime-quality tradeoff in partitioning based multithreaded packing

Runtime-quality tradeoff in partitioning based multithreaded...

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international conference on field programmable logic and applications

作者： Dries Vercruyce Elias Vansteenkiste Dirk Stroobandt ELIS department Computer Systems Lab Ghent Belgium

It takes a long time to generate a configuration for an FPGA starting from a description of a digital circuit in a hardware design language. this configuration should have a high quality so that the FPGA resources are used in an efficient way with the maximum clock frequency and minimizing the power consumption. In this work we present two new packing algorithms that obtain better quality and faster runtimes when compared to the frequently used AAPack packer. the partitioning based methodology allows us to exploit the advantage of multithreading on commodity hardware. Firstly we demonstrate the benefits of our fully partitioning based PartSA packer. Existing packers with a partitioning based approach have problems with the cluster size and bandwidth constraint of the functional blocks. We added a fast simulated annealing step after partitioning to solve these problems. A gain of 26% in total wirelength is obtained while reaching up to 2.3× faster packing runtimes for large circuits on a CPU with four cores. Unfortunately the PartSA packer can not be used for architectures without a complete crossbar in the functional blocks. therefore a second packer is proposed that combines the benefits of partitioning based and seed based packing. MultiPart has up to 4× faster packing runtimes while still having a gain of 20% in total wirelength.

关键词： Delays Runtime field programmable gate arrays Multiprocessor interconnection Video recording Pins

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Comprehensive laser sensitivity profiling and data register bit-flips for cryptographic fault attacks in 65 Nm FPGA 6th

Comprehensive laser sensitivity profiling and data register ...

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6th international conference on Security, Privacy, and Applied Cryptography Engineering, SPACE 2016

作者： He, Wei Breier, Jakub Bhasin, Shivam Jap, Dirmanto Ong, Hock Guan Gan, Chee Lip Lab of Physical Analysis and Cryptographic Engineering Nanyang Technological University Singapore Singapore School of Physical and Mathematical Sciences Nanyang Technological University Singapore Singapore School of Materials Science and Engineering Nanyang Technological University Singapore Singapore Temasek Laboratories Nanyang Technological University Singapore Singapore

ISBN: (纸本)9783319494449

FPGAs have emerged as a popular platform for security sensitive applications. As a practical attack methodology, laser based fault analyses have drawn much attention in the past years due to its superior accuracy in fault perturbation into security-critical Integrated Circuits (ICs). However, due to the insufficient device information, the practical injections work are not so efficient as expected. In this paper, we thoroughly analyze the laser fault injections to data flip-flops, instead of the widely studied configuration memory bits, of a modern nanoscale FPGA. A profiling campaign based on laser chip scan is performed on an exemplary 65 nm Virtex-5 FPGA, through the delayered silicon substrate, to identify the laser sensitivity distribution of the resource array and the fundamental logic cells. the sophisticated flip-flop bit flips are realized by launching fine-grained laser perturbations on an identified Configurable logic Block (CLB) region. the profiled laser fault sensitivity map to FPGA resource significantly facilitate high-precision logic navigation and fault injection in practical cryptographic fault attacks. We show that the observed single- and multiple-bit faults are compatible with most proposed differential or algebraic fault analyses (DFA/AFA). Finally, further discussions on capability of reported fault models to bypass fault countermeasures like parity and dual-rail logic are also given. © Springer international Publishing AG 2016.

关键词： field programmable gate arrays (FPGA)

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Annotation-based finite-state transducers on reconfigurable devices

Annotation-based finite-state transducers on reconfigurable ...

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international conference on field programmable logic and applications

作者： Raphael Polig Kubilay Atasu Christoph Hagleitner theresa Xu Akihiro Nakayama IBM Research - Zurich Rueschlikon Switzerland IBM Systems Toronto Canada IBM Watson Tokyo Japan

With the ever growing amount of unstructured data, high-speed content analysis becomes ever more important. Enabling efficient search functions to help locate specific and relevant information hidden in this big data is a crucial task of today's enterprise systems, and can lead to valuable insights. A key component of content analysis systems are text parsers, which transform unstructured text data into structured information. Cascaded grammars offer a popular and powerful representation of text parsers by enabling the definition of more complex patterns in terms of simpler ones in a hierarchical fashion. this work presents a compilation framework to generate an optimized FPGA pipeline from a cascaded grammar description. We also describe the system integration and the way FPGA-based accelerators can be used as part of larger analysis tasks within Unstructured Information Management Application (UIMA) pipelines. We compare the performance of the hardware-accelerated system and a commercial software implementation using real-life UIMA pipelines from the healthcare domain. We show that the FPGA-accelerated system processes the parsing stage of a UIMA pipeline up to 31 times faster than the software implementation running on a high-end server, which results in an acceleration of up to 5 times for the complete pipeline.

关键词： Grammar Computer architecture Transducers field programmable gate arrays Pipelines Registers Engines

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Resource efficient real-time processing of Contrast Limited Adaptive Histogram Equalization

Resource efficient real-time processing of Contrast Limited ...

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international conference on field programmable logic and applications

作者： Burak Unal Ali Akoglu Department of Electrical and Computer Engineering The University of Arizona Tucson USA

Contextual Contrast Limited Adaptive Histogram Equalization (C-CLAHE) is an effective method for solving the noise amplification effect of the adaptive histogram equalization (AHE), and enhancing the visibility of local details of an image. Even though C-CLAHE has a smaller memory foot print than CLAHE, complexity of the interpolation process increases the computation demand dramatically. therefore, FPGA based implementations have been limited to CLAHE only. In this study we introduce three key modifications to the C-CLAHE, and for the first time make it feasible to implement on a resource limited FPGA. We restructure the method so that the histogram redistribution stage is realized with fewer number of iterations. We implement contrast limitation calculations earlier during the histogram generation stage instead of during the histogram redistribution stage, which reduces the block RAM demand. We finally mathematically derive an alternative interpolation calculation used during the remapping stage, which reduces the computation complexity in terms of required multipliers by a factor of 2×, without sacrificing the image quality. these algorithmic modifications allowed us to reduce the block RAM demand by a factor of 12×, logic block demand by a factor of 6.7× compared to the state of the art FPGA based CLAHE implementation, and achieve real time processing of 640 × 480 images at a rate of 354 frames per second.

关键词： Histograms field programmable gate arrays Random access memory Real-time systems Complexity theory Interpolation Adaptive equalizers

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A survey of AIS-20/31 compliant TRNG cores suitable for FPGA devices

A survey of AIS-20/31 compliant TRNG cores suitable for FPGA...

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international conference on field programmable logic and applications

作者： Oto Petura Ugo Mureddu Nathalie Bochard Viktor Fischer Lilian Bossuet UMR 5516 CNRS Jean Monnet University Saint-Etienne Saint-Etienne France

FPGAs are widely used to integrate cryptographic primitives, algorithms, and protocols in cryptographic systems-on-chip (CrySoC). As a building block of CrySoCs, True Random Number Generators (TRNGs) exploit analog noise sources in electronic devices to generate confidential keys, initialization vectors, challenges, nonces, and random masks in cryptographic protocols. TRNGs aimed at cryptographic applications must fulfill the security requirements defined in the German Federal Bureau for Information Security's (BSI) recommendations AIS-20/31, which has become a de facto standard in Europe. Many TRNG cores have already been published, only a few of which are suitable for FPGAs and even fewer comply with AIS-20/31. Here we present the results of the implementation of AIS-20/31 compliant TRNG cores in three FPGA families: Xilinx Spartan 6, Altera Cyclone V and Microsemi SmartFusion 2. In addition to common design parameters like area, bit rate and power/energy consumption, we compare and discuss the feasibility of generator cores in different FPGAs and the statistical quality of their output. these results will help designers select the best generator and the device family to match the requirements of the data security application. To ensure reproducibility of the results, the open source VHDL code of all generators adapted to individual families can be downloaded from the dedicated web page.

关键词： field programmable gate arrays Generators Clocks Jitter Ring oscillators Entropy Cryptography

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SRI-SURF: A better SURF powered by scaled-RAM interpolator on FPGA

SRI-SURF: A better SURF powered by scaled-RAM interpolator o...

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international conference on field programmable logic and applications

作者： Xijie Jia Kaiyuan Guo Wenqiang Wang Yu Wang Huazhong Yang Kunming Institute of Physics Kunming China E.E. Dept. Tsinghua University Beijing China Microsoft Research Asia Beijing China

Speed-Up Robust Feature (SURF) is an effective algorithm for feature extraction. We propose a novel Scaled-RAM Interpolator (SRI) on FPGA to deal with the high complexity of SURF by introducing two methods. 1) Interpolation of Integral Image (I 3 ) restores the sub-pixel details of image to improve matching precision, and halves the memory access to achieve acceleration; 2) Multi-Scaled RAM (MSR) normalizes the storage allocation by scale to decrease complexity of memory access and reject redundant memory. With SRI, our system achieves better matching precision, higher processing speed, and lower storage occupation. the results of evaluation implemented on Stratix III EP3SL340 FPGA show that 1) our SRI-SURF system performs better in matching than OpenSURF; 2) the system is capable to process 241K feature points per second (PPS), which is about 7× of previous work on FPGA and is comparable to the recent ASIC solution; 3) the maximal frame rate reaches 488FPS at VGA and 72FPS at 1080P, which outperforms designs in other publications; 4) our design is compact, which only occupies about 22% logic resource and about 43% RAM resource at 1080P. the proposed SRI-SURF meets the demand of real-time embedded applications with better precision at high resolution.

关键词： field programmable gate arrays Feature extraction Random access memory Interpolation Algorithm design and analysis IP networks Hardware

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Controller architecture for low-latency access to phase-change memory in OpenPOWER systems

Controller architecture for low-latency access to phase-chan...

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international conference on field programmable logic and applications

作者： A. Prodromakis N. Papandreou E. Bougioukou U. Egger N. Toulgaridis th. Antonakopoulos H. Pozidis E. Eleftheriou University of Patras Rio-Patras Greece IBM Research - Zurich Rüschlikon Switzerland University of Patras Patras GR

Novel forms of nonvolatile memory, such as phase-change memory (PCM), promise low latency and small granularity of read and write access at high storage density. they also feature very high endurance. these characteristics make them highly desirable for emerging high-capacity (hybrid) memory applications such as in-memory databases and in-memory processing. In this work, we present the architecture, implementation and experimental performance results of an FPGA-based PCM memory controller for OpenPOWER servers. the memory controller leverages the Coherent Accelerator Processor Interface (CAPI) of the POWER processor in order to offer low-latency access to the CPU memory space. In addition, the memory controller implements an efficient management protocol that supports a dynamic size of pending read and write requests in order to offer high bandwidth under mixed-type workloads. We describe the architecture and implementation details of the memory controller and we demonstrate its performance using a prototype platform based on different types of OpenPOWER servers equipped with CAPI-enabled FPGA cards. the developed PCM controller is evaluated in terms of sustained data rates (MBps) and access latency (us). Experimental results are based on legacy commercial 90nm PCM chips as well as on accurate HW emulation of next generation PCM chips.

关键词： Phase change materials Nonvolatile memory field programmable gate arrays Servers Memory management Next generation networking Engines

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