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FPGA-based accelerator design from a domain-specific language

FPGA-based accelerator design from a domain-specific languag...

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international conference on field programmable logic and applications

作者： M. Akif Özkan Oliver Reiche Frank Hannig Jürgen Teich Friedrich-Alexander University of Erlangen-Ntirnberg (FAU) Germany

A large portion of image processing applications often come with stringent requirements regarding performance, energy efficiency, and power. FPGAs have proven to be among the most suitable architectures for algorithms that can be processed in a streaming pipeline. Yet, designing imaging systems for FPGAs remains a very time consuming task. High-Level Synthesis, which has significantly improved due to recent advancements, promises to overcome this obstacle. In particular, Altera OpenCL is a handy solution for employing an FPGA in a heterogeneous system as it covers all device communication. However, to obtain efficient hardware implementations, extreme code modifications, contradicting OpenCL's data-parallel programming paradigm, are necessary. In this work, we explore the programming methodology that yields significantly better hardware implementations for the Altera Offline Compiler. We furthermore designed a compiler back end for a domain-specific source-to-source compiler to leverage the algorithm description to a higher level and generate highly optimized OpenCL code. Moreover, we advanced the compiler to support arbitrary bit width operations, which are fundamental to hardware designs. We evaluate our approach by discussing the resulting implementations throughout an extensive application set and comparing them with example designs, provided by Altera. In addition, as we can derive multiple implementations for completely different target platforms from the same domain-specific language source code, we present a comparison of the achieved implementations in contrast to GPU implementations.

关键词： Kernel Hardware Computer architecture Programming field programmable gate arrays Image processing

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Optimizing hardware design for Human Action Recognition

Optimizing hardware design for Human Action Recognition

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international conference on field programmable logic and applications

作者： Xiaoyin Ma Jose Rodriguez Borbon Walid Najjar Amit K. Roy-Chowdhury University of California Riverside CA USA

Human action recognition (HAR) is an important topic in computer vision having a wide range of applications: health care, assisted living, surveillance, security, gaming, etc. Despite significant amount of work having been conducted in this area in recent years, the execution speed still limits real-time applications. Moreover, it is highly desirable to have the compute-intensive feature extraction stage done right at the output of the camera to extract and transfer only action feature in multi-camera network setting and hence reduce network bandwidth requirement. In this work, we first evaluate the possibility to perform feature extraction under reduced precision fixed-point arithmetic to ease hardware resource requirements. We compared the Histogram of Oriented Gradient in 3D (HOG3D) feature extraction with state-of-the-art Convolutional Neural Networks (CNNs) methods and shown the later to be 75× slower than the former. Our experiment shows that by re-training the classifier with reduced data precision, the classification performs as well as the original double-precision floating-point. Based on this result, we implement an FPGA-based HAR feature extraction for near camera processing using fixed-point data representation and arithmetic. this implementation, using a single Xilinx Virtex 6 FPGA, achieves about 70× speedup over multicore CPU. Furthermore, a GPU implementation of HAR is introduced with 80× speedup over CPU (on an Nvidia Tesla K20). Last but not least, a power comparison is presented for the three platforms.

关键词： Feature extraction field programmable gate arrays Histograms three-dimensional displays Cameras Hardware Bandwidth

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Quantifying observability for in-system debug of high-level synthesis circuits

Quantifying observability for in-system debug of high-level ...

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international conference on field programmable logic and applications

作者： Jeffrey Goeders Steven J.E. Wilton Department of Electrical and Computer Engineering University of British Columbia Vancouver Canada

In recent years high-level synthesis (HLS) has seen considerable attention as it promises to increase designer productivity and make custom hardware implementation accessible to software developers. A challenge facing those developing HLS technologies is how to allow users to understand, debug and optimize their final hardware systems. Recently, several techniques have been developed to provide in-system debugging capabilities for HLS circuits. these techniques instrument the user's design with some debugging circuitry to provide observability into the circuit during execution. Due to resource constraints, it is usually infeasible to view all variable values for the entire circuit execution. Rather, instrumentation usually captures only some variable values and for only a portion of the circuit execution. In this paper we present a metric for measuring the observability into an executing HLS circuit. this metric reflects the portion of variable accesses that are available to the user, the duration of execution for which these values are available, as well as accommodating variations in importance between source code variables. this metric can be used to understand how different circuit observation networks can provide the user with different levels of observability into the HLS circuit execution. As a demonstration of the applicability of the metric, we first study differences between recent debugging approaches for HLS circuits, and quantify the level of observability provided by such architectures. We then explore different schemes to select which variables are accessible in the observation network, and measure impact on variable availability and length of captured execution trace.

关键词： Debugging Software Hardware Observability Measurement Computer bugs field programmable gate arrays

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An evaluation on the accuracy of the minimum width transistor area models in ranking the layout area of FPGA architectures

An evaluation on the accuracy of the minimum width transisto...

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international conference on field programmable logic and applications

作者： Farheen Fatima Khan Andy Ye Department of Electrical and Computer Engineering Ryerson University Toronto Canada

this work provides an evaluation on the accuracy of the minimum width transistor area models in ranking the actual layout area of FPGA architectures. Both the original VPR area model and the new COFFE area model are compared against the actual layouts with up to 3 metal layers for the various FPGA building blocks. We found that both models have significant variations with respect to the accuracy of their predictions across the building blocks. In particular, the original VPR model overestimates the layout area of larger buffers and full adders by as much as 34% while underestimate the layout area of smaller buffers and multiplexers by as much as 59% for an overall prediction error variation of 93%. the newer COFFE model also significantly overestimates the layout area of full adders by 13% and underestimates the layout area of multiplexers by a maximum of 58% for a prediction error variation of 71%. Such variations are particularly significant considering sensitivity analyses are not routinely performed in FPGA architectural studies. Our results suggest that such analyses are extremely important in studies that employing the minimum width area models so the tolerance of the architectural conclusions against the prediction error variations can be quantified. Furthermore, an open source version of the layouts of the actual FPGA building blocks should be created, so their actual layout area can be used to achieve a highly accurate ranking of the implementation area of FPGA architectures built upon these layouts.

关键词： Layout field programmable gate arrays Transistors Mathematical model Computer architecture Architecture Multiplexing

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Liquid: Fast placement prototyping through steepest gradient descent movement

Liquid: Fast placement prototyping through steepest gradient...

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international conference on field programmable logic and applications

作者： Elias Vansteenkiste Seppe Lenders Dirk Stroobandt Department of Electronics and Information Systems Ghent University Belgium

FPGA design compilation takes too much time to allow efficient design turnaround times. the largest runtime consuming steps of the compilation are placement and routing. To speed up the FPGA placement process, analytical placement techniques have become more popular in the last decade. Analytical techniques produce a placement in two steps, a placement prototyping step and a refinement step. In this work we focus on fast FPGA placement prototyping. Placement prototypes are also used to obtain fast accurate timing estimations and speed up the design cycle. In conventional analytical placement prototyping techniques the placement problem is formulated as a linear system which is solved several times to find a good legal placement. the most time consuming step of that process is solving the linear system. We show that it is not necessary to exactly solve this system, but that it is sufficient to optimize the placement following the steepest gradient descent in between legalization phases. this technique is implemented in our new placement tool called Liquid. In Liquid each block's position is updated several times following an accelerated gradient simulation. We compare this new technique with conventional analytical placement. the Titan23 designs and the Stratix IV FPGA are used for benchmarking. the net effect is that the runtime can be reduced by 2× on average compared to conventional analytical placement without losing any quality.

关键词： Liquids Runtime field programmable gate arrays Linear systems Timing Optimization Law

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Survey of domain-specific languages for FPGA computing

Survey of domain-specific languages for FPGA computing

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international conference on field programmable logic and applications

作者： Nachiket Kapre Samuel Bayliss School of Computer Science and Engineering Nanyang Technological University Singapore Department of Electrical and Electronic Engineering Imperial College London London

High-performance FPGA programming has typically been the exclusive domain of a small band of specialized hardware developers. they are capable of reasoning about implementation concerns at the register-transfer level (RTL) which is analogous to assembly-level programming in software. Sometimes these developers are required to push further down to manage even lower levels of abstraction closer to physical aspects of the design such as detailed layout to meet critical design constraints. In contrast, software programmers have long since moved away from textual assembly-level programming towards relying on graphical integrated development environments (IDEs), high-level compilers, smart static analysis tools and runtime systems that optimize, manage and assist the program development tasks. Domain-specific languages (DSLs) can bridge this productivity gap by providing higher levels of abstraction in environments close to the domain of application expert. DSLs carefully limit the set of programming constructs to minimize programmer mistakes while also enabling a rich set of domain-specific optimizations and program transformations. With a large number of DSLs to choose from, an inexperienced FPGA user may be confused about how to select an appropriate one for the intended domain. In this paper, we review a combination of legacy and state-of-the-art DSLs available for FPGA development and provide a taxonomy and classification to guide selection and correct use of the framework.

关键词： field programmable gate arrays Hardware DSL Hardware design languages Software Programming Productivity

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Stress-aware routing to mitigate aging effects in SRAM-based FPGAs

Stress-aware routing to mitigate aging effects in SRAM-based...

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international conference on field programmable logic and applications

作者： Behnam Khaleghi Behzad Omidi Hussam Amrouch Jörg Henkel Hossein Asadi Department of Computer Engineering Sharif University of Technology Tehran Chair for Embedded Systems Karlsruhe Institute of Technology Germany

Continuous shrinking of transistor size to provide high computation capability along with low power consumption has been accompanied by reliability degradations due to e.g., aging phenomenon. In this regard, with huge number of configuration bits, field-programmable Gate Arrays (FPGAs) are more susceptible to aging since aging not only degrades the performance, it may additionally result in corrupting the configuration cells and thus causing permanent circuit malfunctioning. While several works have investigated the aging effects in Look-Up Tables (LUTs), the routing fabric of these devices is seldom studied - even though it contributes to the majority of FPGAs' resources and configuration bits. Furthermore, there is a high prospect that errors in its state to propagate to the device outputs. In this paper, we first investigate aging effects in the routing fabric of FPGAs with respect to performance and reliability degradations. Based on this investigation, we enhance the conventional routing algorithm to mitigate the impact of aging by increasing the recovery time (i.e., the mechanism used to heal aging-induced defects) of transistors used in the routing resources. We examine our proposed method as reduction in stress time and required guardband to protect against aging in the routing fabric, as well as in improving the FPGA's lifetime. Our experiments show that the proposed method reduces the average stress time and aging-induced delay of routing resources by 41% and 18.3%, respectively. this, in turn, leads to improving the device lifetime by 130% compared to baseline routing. the proposed method can be applied by simple amending of conventional routing algorithms. thus, it incurs negligible delay overhead.

关键词： Aging Routing field programmable gate arrays Table lookup Stress Delays Transistors

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Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA

Scalable and modularized RTL compilation of Convolutional Ne...

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international conference on field programmable logic and applications

作者： Yufei Ma Naveen Suda Yu Cao Jae-sun Seo Sarma Vrudhula Computer and Energy Engineering Arizona State University Tempe USA Decision Systems Engineering Arizona State University Tempe USA

Despite its popularity, deploying Convolutional Neural Networks (CNNs) on a portable system is still challenging due to large data volume, intensive computation and frequent memory access. Although previous FPGA acceleration schemes generated by high-level synthesis tools (i.e., HLS, OpenCL) have allowed for fast design optimization, hardware inefficiency still exists when allocating FPGA resources to maximize parallelism and throughput. A direct hardware-level design (i.e., RTL) can improve the efficiency and achieve greater acceleration. However, this requires an in-depth understanding of both the algorithm structure and the FPGA system architecture. In this work, we present a scalable solution that integrates the flexibility of high-level synthesis and the finer level optimization of an RTL implementation. the cornerstone is a compiler that analyzes the CNN structure and parameters, and automatically generates a set of modular and scalable computing primitives that can accelerate various deep learning algorithms. Integrating these modules together for end-to-end CNN implementations, this work quantitatively analyzes the complier's design strategy to optimize the throughput of a given CNN model with the FPGA resource constraints. the proposed methodology is demonstrated on Altera Stratix-V GXA7 FPGA for AlexNet and NIN CNN models, achieving 114.5 GOPS and 117.3 GOPS, respectively. this represents a 1.9× improvement in throughput when compared to the OpenCL-based design. the results illustrate the promise of the automatic compiler solution for modularized and scalable hardware acceleration of deep learning.

关键词： field programmable gate arrays Convolution Hardware Kernel Acceleration Memory management Algorithm design and analysis

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AdapNoC: A fast and flexible FPGA-based NoC simulator

AdapNoC: A fast and flexible FPGA-based NoC simulator

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international conference on field programmable logic and applications

作者： Hadi Mardani Kamali Shahin Hessabi Sharif University of Technology Tehran Tehran IR Department of Computer Engineering Sharif University of Technology Tehran Iran

Network on Chip (NoC) is the most common interconnection platform for multiprocessor systems-on-chips (MPSoCs). In order to explore the design space of this platform, we need a high-speed, cycle-accurate, and flexible simulation tool. In this paper, we present AdapNoC, a configurable cycle-accurate FPGA-based NoC simulator, which can be configured via software. A wide range of parameters are configurable in FPGA side of the proposed simulator, and the software side is implemented on an embedded soft-core processor. We transfer some parts of simulator, such as Traffic Generators (TGs) and Traffic Receptors (TRs), to software side without any degradation in simulation speed. Moreover, we implement a dual-clock architecture as an innovation in virtualization methodology, which is also capable to share idle time-slots, which helps not only simulate bigger NoCs, but also reduce simulation time drastically. Also, by employing a traffic aggregator architecture, AdapNoC provides table-based adaptive routing algorithm as a configurable parameter in router microarchitecture. We evaluate simulation time of AdapNoC by using Xilinx Virtex-6 XC6VLX240T, and demonstrate 53x-180x speed-up against BOOKSIM. Also, due to our proposed virtualization, and TGs and TRs migration to software side, we can implement a 64-node non-virtualized or a 1024-node virtualized mesh network in only %72 of Xilinx Virtex-6 XC6VLX240T resources.

关键词： field programmable gate arrays Routing Software Virtualization Computer architecture Adaptation models Time division multiple access

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Power Analysis of Energy Efficient DES Algorithm and Implementation on 28nm FPGA 19

Power Analysis of Energy Efficient DES Algorithm and Impleme...

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第十五届分布式计算及其应用国际学术研讨会

作者： Vandana thind Bishwajeet Pandey D M Akbar Hussain Department of Electronic And Communication Engineering Chitkara University Department of Energy Technology Aalborg University

ISBN: (纸本)9781509035946

in this work,we have done power analysis of Data Encryption Standard(DES) algorithm using Xilinx ISE software development *** have analyzed the amount of power utilized by selective components on board i.e.,FPGA Artix-7,where DES algorithm is *** components taken into consideration are clock power,logic power,signals power,IOs power,leakage power and supply power(dynamic and quiescent).We have used four different WLAN frequencies(2.4 GHz,3.6 GHz,4.9 GHz,and 5.9 GHz) and four different IO standards like HSTL-I,HSTL-II,HSTL-II-18,HSTL-I-18 for power *** have achieved13-47% saving in power at different frequencies and with different energy efficient HSTL IO *** calculated the percentage change in the IO power with respect to the mean values of IO power at four different *** notified that there is minimum of-37.5% and maximum of +35.8% *** work helps to design and implement DES algorithm with maximum power efficiency.

关键词： Standards Algorithm design and analysis field programmable gate arrays Clocks System-on-chip Energy efficiency Software algorithms

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