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Estimating Circuit Delays in FPGAs after Technology Mapping 25

Estimating Circuit Delays in FPGAs after Technology Mapping

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25th international conference on field programmable logic and applications

作者： Severens, Berg Vansteenkiste, Elias Heyse, Karel Stroobandt, Dirk Univ Ghent Dept Elect & Informat Syst Comp Syst Lab Hardware & Embedded Syst Team B-9000 Ghent Belgium

ISBN: (纸本)9781467381239

An FPGA implementation requires a significant effort of the hardware designer, who optimizes FPGA designs by going through many time-consuming CAD flow iterations. these iterations provide two types of feedback: (1) the FPGA performance and (2) the identification of the parts having the highest impact on the FPGA performance. Both depend on the wirelength behavior. Studies have been dedicated to the estimation of local [5] and global [4] wirelengths, but to our knowledge both performance estimations and identification of the critical zone are not present in literature. therefore this paper, firstly, presents a comparison of three performance estimation techniques: logic depth, Monte Carlo simulation and fast placement (ordered from low to high accuracy and runtime). Secondly, four methods identifying the critical zone are compared. Results show that Monte Carlo simulations provide a good identification of the parts having the highest impact on the performance. We conclude that Monte Carlo simulations provide useful feedback within a short runtime (about 30 times faster than placement), reducing the time-tomarket of FPGA implementations.

关键词： field programmable gate arrays critical zone Monte Carlo technique Performance Evaluation Runtime placement HIGH IMPACT iterative methods IMPACT PROPERTIES

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Accurate Power Analysis for Near-V_t RRAM-based FPGA 25

Accurate Power Analysis for Near-<i>V<sub>t</sub></i> RRAM-b...

引用

25th international conference on field programmable logic and applications

作者： Tang, Xifan Gaillardon, Pierre-Emmanuel De Micheli, Giovanni Ecole Polytech Fed Lausanne Lausanne Switzerland

ISBN: (纸本)9781467381239

Resistive Random Access Memory (RRAM)-based FPGA architectures employ RRAMs not only as memories to store the configuration but embed them in the datapaths of programmable routing resources to propagate signals with improved performances. Sources of power consumption have been intensively studied for conventional Static Random Access Memories (SRAM)-based FPGAs. However, very limited works focused so far on studying the power characteristics of RRAM-based FPGAs. In this paper, we first analyze the power characteristics of RRAM-based multiplexer at circuit level and then use electrical simulations to study power consumption of RRAM-based FPGA architectures. Experimental results show that RRAM-based FPGAs achieve a Power-Delay Product reduced by 50% compared to SRAM-based FPGA at nominal voltage and 20% compared to near-V-t SRAM-based FPGA, respectively.

关键词： field programmable gate arrays (FPGA)

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An Efficient Reconfigurable Architecture by Characterizing Most Frequent logic Functions 25

An Efficient Reconfigurable Architecture by Characterizing M...

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25th international conference on field programmable logic and applications

作者： Ahmadpour, Iman Khaleghi, Behnam Asadi, Hossein Sharif Univ Technol Dept Comp Engn Tehran Iran

ISBN: (纸本)9781467381239

Generous flexibility of Look-Up Tables (LUTs) in implementing arbitrary functions comes with significant performance and area overheads compared with their Application-Specific Integrated Circuit (ASIC) equivalent. One approach to alleviate such overheads is to use less flexible logic elements capable to implement majority of logic functions. In this paper, we first investigate the most frequently used functions in standard benchmarks and then design a set of less-flexible but area-efficient logic cells, called Hard logics (HL). Since higher input functions have diverse classes, we leverage Shannon decomposition to break them into smaller ones to either reduce the HL design space complexity or attain asymmetric low input functions. A heterogeneous LUT-HL architecture and a mapping scheme are also proposed to attain maximum logic resource usage. Experimental results on MCNC benchmarks demonstrate that the proposed architecture reduces area-delay product by 13% and 36% as compared to LUT4 and LUT6 based FPGAs, respectively. Considering the same area budget, our proposed architecture improves performance by 17% and 2% as compared to LUT4 and LUT6 based FPGAs.

关键词： logic functions Formal logic Reconfigurable architectures application specific integrated circuits input function BENCHMARKS Building construction LIPC gene ARCHITECTURE hectolitre

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POWER-EFFICIENT RANGE-MATCH-BASED PACKET CLASSIFICATION ON FPGA 25

POWER-EFFICIENT RANGE-MATCH-BASED PACKET CLASSIFICATION ON F...

引用

25th international conference on field programmable logic and applications

作者： Qu, Yun R. Prasanna, Viktor K. Univ Southern Calif Ming Hsieh Dept Elect Engn Los Angeles CA 90089 USA

ISBN: (纸本)9781467381239

Packet classification is a kernel application performed at network routers. Many classification engines are optimized for prefix and exact match, while a range-to-prefix translation can lead to rule set expansion. Under limited power budget, it is challenging to achieve high classification throughput. In this paper, we present a high-performance and power-efficient packet classification engine on FPGA. We construct a modular Processing Element ( PE);each PE compares a stride of the input packet header against a stride of a range boundary. We concatenate multiple PEs into a systolic array. Efficient power optimization techniques including self-enabled power gating and entropy-based scheduling are explored on our architecture. Experimental results show that, for 4 K 15-field rule sets, our prototype on a state-of-the-art FPGA can achieve 250 Million Packets Per Second (MPPS) throughput. Using the proposed power optimization techniques, our classification engine consumes 30 % of the power without sacrificing the throughput.

关键词： packet classification field programmable gate arrays power budget Energy sources Engines throughput Power (Psychology)

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A Variable Length Hash Method for Faster Short Read Mapping on FPGA 25

A Variable Length Hash Method for Faster Short Read Mapping ...

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25th international conference on field programmable logic and applications

作者： Sogabe, Yoko Maruyama, Tsutomu Univ Tsukuba Syst & Informat Engn 1-1-1 Ten Nou Dai Tsukuba Ibaraki 3058573 Japan

ISBN: (纸本)9781467381239

Short read mapping is a process to align the short reads, which are fixed-length fragments of the target genome, to a given reference genome to identify the mutations in the target genome. Because of the rapid development of Next Generation Sequencing (NGS) technologies, faster short read mapping is required. In this paper, we propose a variable length hash method to further accelerate FPGA short read mapping systems. In the hash-based short read mapping algorithms, a fixed length sub-string of each short read, called seed, is used as the key. However, many different seeds are mapped into the same hash slots because of the high ununiformity of the human genome, and many fruitless key comparisons are performed. To equalize the slot size, we propose an optimized hash function that changes the bit masks adaptively. With this approach, it is possible to improve the performance of all FPGA short read mapping systems based on hash functions. the performance for the comparison in our FPGA system on a Xilinx XC7VX690T and XC6VLX240T can be improved two-times, and the total performance outperforms any existing FPGA systems.

关键词： field programmable gate arrays (FPGA)

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An LZ77-Style Bit-Level Compression for Trace Data Compaction 25

An LZ77-Style Bit-Level Compression for Trace Data Compactio...

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25th international conference on field programmable logic and applications

作者： Irrgang, Kai-Uwe Preusser, thomas B. Brandenburg Tech Univ Cottbus Senftenberg Inst Med Technol Cottbus Germany Tech Univ Dresden Inst Comp Engn Dresden Germany

ISBN: (纸本)9781467381239

Online tracing is a powerful technique for monitoring and debugging embedded processors. the amount of data produced by tracing is enormous. thus, an on-the-fly trace data reduction close by its source is extremely valuable. Trigger-driven filtering and a compressed trace representation are popular measures to take. While effective methods for the compression of branch target addresses in instruction traces are known, modern processors also produce extensive execution bit streams to log the execution of conditional instructions. this paper proposes an LZ77-style compressor for these bit streams. In contrast to classic implementations, it operates on the bit level. It is demonstrated that this compressor is effective even when using a small dictionary. this allows an implementation within an FPGA close by the source or even on the same chip as the trace source. It is also shown that the compressor can keep pace with practically relevant trace data sources.

关键词： Data compression Compressors Bit Level level compression Trace bit stream Legal Executions data reduction Data sources field programmable gate arrays PROCESSOR Binary digits instruction tracing compression

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Wotan: A Tool for Rapid Evaluation of FPGA Architecture Routability Without Benchmarks 25

Wotan: A Tool for Rapid Evaluation of FPGA Architecture Rout...

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25th international conference on field programmable logic and applications

作者： Petelin, Oleg Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9781467381239

FPGA routing architectures consist of routing wires and programmable switches which together account for a significant portion of the fabric delay and area. Routing architectures have traditionally been evaluated using a full CAD flow with a suite of benchmark circuits. While the results of such a flow can be accurate, CAD tools are often tuned to a specific architecture type and can take a long time to run which prohibits quick exploration of different architectures early in the design process. In this paper we present an alternative approach that quickly estimates routability for a wide range of architectures without the use of benchmark circuits. Our new routability predictor first assigns congestion probabilities to the architecture's routing resources based on demand estimates found via efficient path enumeration through the routing graph. Next, we compute the probabilities of successfully routing different source/sink connections and finally we combine them to assign an overall routability score. We describe our predictor and present routability estimates for a range of 6-LUT and 4-LUT architectures, showing reasonable agreement with routability results from the full VPR CAD flow in much less CPU time.

关键词： ARCHITECTURE BENCHMARKS Network routing Building construction design process field programmable gate arrays Computer-Aided Design DFFB gene CPU time

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Hoplite: Building Austere Overlay NoCs for FPGAs 25

Hoplite: Building Austere Overlay NoCs for FPGAs

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25th international conference on field programmable logic and applications

作者： Kapre, Nachiket Gray, Jan Nanyang Technol Univ 50 Nanyang Ave Singapore Singapore Gray Res LLC Bellevue WA USA

ISBN: (纸本)9781467381239

Customized unidirectional, bufferless, deflectionrouted torus networks can outperform classic, bidirectional, buffered mesh networks for single-flit-oriented FPGA applications by as much as 1.5x (best achievable throughputs for a 10 x 10 system) or 2.5x (allocating same FPGA resources to both NoCs) for uniform random traffic. We present Hoplite, an efficient, lightweight, fast FPGA overlay NoC that is designed to be small and compact by (1) eliminating input buffers, and (2) reducing the cost of switch crossbar that have traditionally limited speeds and imposed heavy resource costs in conventional FPGA overlay NoCs. We implement bufferless deflection routing cheaply, requiring the generation of only output multiplexer controls and no backpressure handshakes. Additionally, we use directional channels that help reduce crossbar cost by restricting the number of inputs to the crossbar to three instead of four. When compared to buffered mesh switches, FPGA-based deflection routers are approximate to 3.5x smaller (HLS-generated switch) and 2.5x faster (clock period) for 32b payloads. In a separate experiment, we hand-crafted a prototype RTL version of our switch with RLOCS that requires only 60 LUTs and 100 FFs per router and runs at 2.9 ns.

关键词： field programmable gate arrays (FPGA)

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Limits of FPGA Acceleration of 3D Green's Function Computation for Geophysical applications 25

Limits of FPGA Acceleration of 3D Green's Function Computati...

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25th international conference on field programmable logic and applications

作者： Kapre, Nachiket Kumar, Jayakrishnan Selva Gupta, Parjanya Masuti, Sagar Barbot, Sylvain Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore Nanyang Technol Univ Earth Observ Singapore Singapore 639798 Singapore

ISBN: (纸本)9781467381239

FPGA-based accelerators can outperform multi-core, GPU and Xeon Phi based platforms by at as much as 2.8x for 3D Green's Function processing in geophysics while delivering superior energy efficiency. FPGAs can efficiently implement a complex mixture of compute patterns that include data-parallelism, reductions, dataflow and streaming computations using spatial parallelism to deliver these speedups and power benefits. Since 3D Green's Function is highly-parallel but communication bound, we optimize the FPGA implementation by considering loop restructuring and tiling optimizations to minimize and regularize off-chip accesses. Furthermore, we configure the FPGA to implement the key compute intensive kernels at double-precision as well as single-precision to exploit the uncertainty in measurements of earthquake monitoring sensors. For 512x512x512 problem size, the Xilinx SX475T (Maxeler MAX3) outperforms the fastest architecture by 1.1-1.4x (double-precision), 2.2-2.8x (single-precision) with 1.2x better energy efficiency.

关键词： Green's function double precision field programmable gate arrays geophysics Energy efficiency single precision measurement uncertainty

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Automatic Support for Multi-Module Parallelism from Computational Patterns 25

Automatic Support for Multi-Module Parallelism from Computat...

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25th international conference on field programmable logic and applications

作者： George, Nithin Lee, HyoukJoong Novo, David Owaida, Muhsen Andrews, David Olukotun, Kunle Ienne, Paolo Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland Stanford Univ Pervas Parallelism Laboratory Stanford CA 94305 USA Univ Arkansas Dept Comp Sci & Comp Engn Fayetteville AR 72701 USA

ISBN: (纸本)9781467381239

field programmable Gate Arrays (FPGAs) can be customized into application-specific architectures to achieve high performance and energy-efficiency. Unfortunately, they are yet to gain significant adoption by application developers due to their low-level programming model. Moreover, to obtain good performance in an FPGA design, one often needs to correctly parallelize computation and balance the computational throughput with the available data access bandwidth. To address the programming model problem, recent efforts have focused on composing applications out of parallel computational patterns, such as map, reduce, zipWith and foreach, and leveraging the properties of these patterns to generate highly parallel hardware modules capable of high performance. In this work, we focus on the problem of further improving the performance and show that we can utilize the knowledge of how data is consumed and produced by these computational patterns in conjunction with the information of the system architecture to automatically parallelize computations across multiple hardware modules. To achieve this, we automatically infer synchronization needs arising due to parallelization and generate a complete system that can obtain high performance for a given application. We evaluate our approach using seven applications from different domains and show that our automatically generated designs achieve performance improvements ranging from 1.8 to 9.4 times.

关键词： HIGH-PERFORMANCE hardware module AUTOMATIC multi modules field programmable gate arrays application developer Building systems parallelization Synclitism parallelism

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