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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Monther Abusultan Sunil P Khatri ECE Department Texas A&M University College Station TX

field programmable gate arrays (FPGAs) are the implementation platform of choice when it comes to design flexibility. However, SRAM-based FPGAs suffer from high power consumption, prolonged boot delays (due to the volatility of the configuration bits), and a significant area overhead (due to the use of 5T SRAM cells for the configuration bits). Floating gate (flash) based FPGAs can avert these problems. this paper presents a study of flash-based FPGA designs (both static and dynamic), and presents the tradeoff of delay, power dissipation and energy consumption of the various designs. Our work differs from previously proposed flash-based FPGAs, since we embed the flash transistors (which store the configuration bits) directly within the logic and interconnect fabrics. We also present a detailed description of how the programming of the configuration bits is accomplished. Our delay and power estimates are derived from circuit level simulations. Our proposed static flash-based LUT structure yields 10% faster operation, 12% lower dynamic power dissipation, 21% lower energy consumption and 29% lower static power dissipation compared to a traditional SRAM-based LUT. We also show that, for high performance applications, a dynamic flash-based LUT can achieve further performance improvements (32% lower delay) with higher energy consumption (37% higher) compared to an SRAM-based LUT. We also show that a flash-based interconnect structure provides 89% lower delay and 71% lower overall power consumption compared to the traditional interconnect structure used in SRAM-based FPGAs.

关键词： field programmable gate arrays Table lookup logic gates Transistors Delays Nonvolatile memory Integrated circuit interconnections

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Performance analysis of transistor-based circuits through TAMAMS Web: From bulk to molecular devices

Performance analysis of transistor-based circuits through TA...

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international conference on Electronic Devices, Systems and applications (ICEDSA)

作者： Izhar Hussain Fabrizio Riente Massimo Ruo Roch Gianluca Piccinini Mariagrazia Graziano Department of Electronics and Telecommunications Politecnico di Torino Italy

ISBN: (纸本)9781509053070

To meet the challenges associated with transistor scaling and short channel devices, the structure of MOS devices has undergone an incredible evolution. From Bulk devices, technology has shifted through Silicon-On-Insulator (SOI) devices, reaching now FinFET transistors, the next steps in the evolutionary path are represented by Gate-All-Around (GAA) and Molecular Transistors. Using analytical compact models for standard (BULK, SOI, FinFET) and emerging devices (GAA, Molecular FET (MOLFET)), it is possible to predict the system level performance of future NANO electronic circuits. In this work, we show how circuit's performance can be predicted and analyzed at system level using our tool, TAMTAMS Web. Starting from Bulk transistors down to a nanometer scale Molecular FET, TAMTAMS Web incorporates models to analyze device quantities (Drive current, Subthresold current...) up to system level. We have developed a compact model of Virtex 4 FPGA CLB block that is used as benchmark. the work here presented not only highlights the potentialities of TAMTAMS, but it also provides useful hints on the evolution of transistor based technology.

关键词： Transistors logic gates field programmable gate arrays Gallium arsenide Semiconductor device modeling Integrated circuit modeling Performance evaluation

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A real-time FPGA-based solution for binary image thinning

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Lecture Notes in Electrical Engineering 2016年 351卷 169-174页

作者： Davalle, Daniele Carnevale, Berardino Saponara, Sergio Fanucci, Luca Terreni, Pierangelo Department of Information Engineering University of Pisa Via Caruso 16 Pisa56122 Italy

ISBN: (纸本)9783319202266

this paper presents an optimized FPGA implementation for real-time binary image thinning algorithm. the reference thinning technique is based on iterated comparisons with a set of eight 3×3 binary masks. In the proposed architecture, the processing logic and the internal memory are implemented in a way that themask matching on each 3×18 image segment can be done in parallel within a single clock cycle. this optimization entails a reduction of more than one order of magnitude in terms of execution cycles with respect to the original algorithm. the algorithm was implemented on an ALTERA Stratix II EP2S30 FPGA. the resource occupation of the thinning block and the dedicated memory controllers is 4% at 100MHz clock frequency. the proposed solution produces the output in 0.03 s on a standard PAL 720 × 576, allowing for further real-time processing. © Springer international Publishing Switzerland 2016.

关键词： field programmable gate arrays (FPGA)

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Review of NoC-Based FPGAs Architectures 5

Review of NoC-Based FPGAs Architectures

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5th international conference on Energy Aware Computing Systems & applications (ICEAC)

作者： Salaheldin, Alaa Abdallah, Karim Gamal, Noha Mostafa, Hassan Cairo Univ Elect & Commun Engn Dept Giza 12613 Egypt AUC Ctr Nanoelect & Devices New Cairo 11835 Egypt Zewail City Sci & Technol New Cairo 11835 Egypt

ISBN: (纸本)9781479917723

Nowadays, FPGAs serve as fields programmable Systems on Chip (FPSoC) and are widely used to implement computationally intensive world applications. As the number of components in FPSoCs increases, the interconnect schemes based on Network on Chip (NoC) approach are increasingly used to overcome the problems of traditional bus based and point-to-point interconnect scheme. In this paper, we review several designs based on their contributions, architectures, implementations and future works. We also made our comparison between three of these routes to analyze the effect of varying the number of Virtual Channels (VCs), flit data width and buffer depth on the operating frequency, logic Look-Up Tables (LUTs) and registers to help choosing the appropriate NoC based on system requirements.

关键词： field programmable gate arrays Network topology Ports (Computers) Registers Routing Table lookup field programmable gate arrays Table lookup Registers Network topology Network routing ARCHITECTURE system requirements

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CoRAM++: Supporting data-structure-specific memory interfaces for FPGA computing 25

CoRAM++: Supporting data-structure-specific memory interface...

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25th international conference on field programmable logic and applications, FPL 2015

作者： Weisz, Gabriel Hoe, James C. Carnegie Mellon University PittsburghPA United States

ISBN: (纸本)9780993428005

Facilitating DRAM access is an essential part of an application programming environment for FPGA computing. Existing FPGA application programming environments primarily focus on support for simple, regular memory access patterns, such as block copy and streaming. this paper presents CoRAM++, a programming environment for FPGA computing that is based on an extensible set of data-structure-specific memory interfaces. CoRAM++ supports complex data structures, such as multidimensional arrays and linked lists, in addition to simple data access patterns. CoRAM++ defines an appropriate application-level interface for each supported data structure, and provides a specialized soft-logic implementation of the supporting datapath to memory We evaluated the effectiveness of the CoRAM++ data-structure-specific approach in three application scenarios based on streams, multi-dimensional arrays and linked lists. Our results show that the CoRAM++ programming environment can offer convenient application-level interfaces without penalizing DRAM access performance. © 2015 Imperial College.

关键词： field programmable gate arrays (FPGA)

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FPGA based nonlinear Support Vector Machine training using an ensemble learning 25

FPGA based nonlinear Support Vector Machine training using a...

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25th international conference on field programmable logic and applications, FPL 2015

作者： Rabieah, Mudhar Bin Bouganis, Christos-Savvas Department of Electrical and Electronic Engineering Imperial College London London United Kingdom

ISBN: (纸本)9780993428005

Support Vector Machines (SVMs) are powerful supervised learning methods in machine learning. However, their applicability to large problems has been limited due to the time consuming training stage whose computational cost scales quadratically with the number of examples. In this work, a complete FPGA-based system for nonlinear SVM training using ensemble learning is presented. the proposed framework builds on the FPGA architecture and utilizes a cascaded multi-precision training flow, exploits the heterogeneity within the training problem by tuning the number representation used, and supports ensemble training tuned to each internal memory structure so to address very large datasets. Its performance evaluation shows that the proposed system achieves more than an order of magnitude better results compared to state-of-the-art CPU and GPU-based implementations. © 2015 Imperial College.

关键词： field programmable gate arrays (FPGA)

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Ultra-Fast NoC Emulation on a Single FPGA

Ultra-Fast NoC Emulation on a Single FPGA

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25th international conference on field programmable logic and applications

作者： thiem Van Chu Sato, Shimpei Kise, Kenji Tokyo Inst Technol Dept Comp Sci Tokyo Japan Tokyo Inst Technol Global Sci Informat & Comp Ctr Tokyo Japan

ISBN: (纸本)9781467381239

Network-on-Chip (NoC) has become the de facto on-chip communication architecture for many-core systems. this paper proposes novel methods for emulating large-scale NoC designs on a single FPGA. Since FPGAs offer a highly parallel platform, FPGA-based emulation can be much faster than the software-based approach. However, emulating NoC designs with up to thousands of nodes is a challenging task due to the FPGA capacity constraints. We first describe how to accurately model synthetic workloads on FPGA by separating the time of the emulated network and the times of the traffic generation units. We next present a novel use of time-multiplexing in emulating the entire network using several physical nodes. Finally, we show the basic steps to apply the proposed methods to emulate different NoC architectures. the proposed methods enable ultra-fast emulations of large-scale NoC designs with up to thousands of nodes using only on-chip resources of a single FPGA. In particular, more than 5,000x simulation speedup over BookSim, a widely used software-based NoC simulator, is achieved.

关键词： field programmable gate arrays simulating Ganglia basic sequence system-on-chip

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CNN-MERP: An FPGA-based memory-efficient reconfigurable processor for forward and backward propagation of convolutional neural networks

CNN-MERP: An FPGA-based memory-efficient reconfigurable proc...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Xushen Han Dajiang Zhou Shihao Wang Shinji Kimura Production and Systems Waseda University Kitakyushu Fukuoka Japan

Large-scale deep convolutional neural networks (CNNs) are widely used in machine learning applications. While CNNs involve huge complexity, VLSI (ASIC and FPGA) chips that deliver high-density integration of computational resources are regarded as a promising platform for CNN's implementation. At massive parallelism of computational units, however, the external memory bandwidth, which is constrained by the pin count of the VLSI chip, becomes the system bottleneck. Moreover, VLSI solutions are usually regarded as a lack of the flexibility to be reconfigured for the various parameters of CNNs. this paper presents CNN-MERP to address these issues. CNN-MERP incorporates an efficient memory hierarchy that significantly reduces the bandwidth requirements from multiple optimizations including on/off-chip data allocation, data flow optimization and data reuse. the proposed 2-level reconfigurability is utilized to enable fast and efficient reconfiguration, which is based on the control logic and the multiboot feature of FPGA. As a result, an external memory bandwidth requirement of 1.94MB/GFlop is achieved, which is 55% lower than prior arts. Under limited DRAM bandwidth, a system throughput of 1244GFlop/s is achieved at the Vertex UltraScale platform, which is 5.48 times higher than the state-of-the-art FPGA implementations.

关键词： Kernel Bandwidth Memory management throughput field programmable gate arrays Backpropagation Neural networks

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An efficient FPGA implementation of the Harris Corner feature detector 14

An efficient FPGA implementation of the Harris Corner featur...

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14th IAPR international conference on Machine Vision applications (MVA)

作者： Chao, Tak Lon Wong, Kin Hong Chinese Univ Hong Kong Dept Elect Engn Hong Kong Hong Kong Peoples R China Chinese Univ Hong Kong Dept Comp Sci & Engn Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9784901122146

In computer vision, the Harris corner feature detector is one of the most essential early steps in many useful applications such as 3-D reconstruction. However, if it is implemented in software, the resulting code is probably not able to be executed in real time under low cost mobile processors. this paper proposes an efficient hardware approach that offloads the repetitive feature extraction procedures into logic gates hence the solution is low cost to produce and low power to operate compared to its software counterpart. In this project, the system is built and tested on a popular prototyping FPGA (field programmable Gate Arrays) platform (Zed-board) with a small FPGA device. the experiments and demos show that the speed and accuracy of the feature detector are good enough for many real world applications.

关键词： logic gates

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An automated technique to generate relocatable partial bitstreams for Xilinx FPGAs 25

An automated technique to generate relocatable partial bitst...

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25th international conference on field programmable logic and applications, FPL 2015

作者： Oomen, Roel Nguyen, Tuan Kumar, Akash Corporaal, Henk

ISBN: (纸本)9780993428005

Partial reconfiguration is a technique used to increase the flexibility of an FPGA-based system by reprogramming parts of the system dynamically without interrupting the operation of the other modules. Despite the runtime benefits offered by partially reconfigurable (PR) systems, creating and storing partial bitstreams (PBs) are becoming major concerns for system architects when the numbers of reconfigurable partitions (RPs) and PR modules (PRMs) increase. It takes significant amount of time to generate the PBs for PR systems with large number of RPs and PRMs. More importantly, when the mapping relationship between PRMs and RPs is many-to-many, several almost-identical PBs of one PRM must be stored separately which leads to inefficient utilization of the memory storage. therefore, bitstream relocation is drawing interests from the research community as a viable solution. Yet almost none of the works are able to demonstrate a coherent method to not only create relocatable PBs for complex and large PRMs in variable-size RPs but also how to do that automatically to free the designer from the tedious and error prone manual processes. In this paper, we propose a new technique to fill that gap. the method is successfully developed for Xilinx Virtex 7 devices using Vivado design tool flow. © 2015 Imperial College.

关键词： field programmable gate arrays (FPGA)

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