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检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

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Placing partially reconfigurable stream processing applications on FPGAs

Placing partially reconfigurable stream processing applicati...

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international conference on field programmable logic and applications

作者： Nicolae Bogdan Grigore Dirk Koch University of Manchester

Finding placement locations for modules on an FPGA in a limited amount of time is a crucial task that determines the efficiency of a dynamic partially reconfigurable system. In this work, we will define a placement method based on transforming the inherent two dimensional (2D) structure of the FPGA into a one dimensional string and employing string matching. Moreover, our model is suited to compute a module placement over multiple chained reconfigurable regions. Our algorithm is based on a hybrid approach consisting of an offline precompute phase at design-time which in turn is used to speed-up module placement at run-time.

关键词： field programmable gate arrays Computational modeling Algorithm design and analysis Libraries Computer architecture Heuristic algorithms Clustering algorithms

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A technology mapper for depth-constrained FPGA logic cells

A technology mapper for depth-constrained FPGA logic cells

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international conference on field programmable logic and applications

作者： Zhenghong Jiang Grace Zgheib Colin Yu Lin David Novo Zhihong Huang Liqun Yang Haigang Yang Paolo Ienne System on Programmable Chip Research Department Institute of Electronics Chinese Academy of Sciences Beijing China Ecole Polytechnique Federale de Lausanne (EPFL) School of Computer and Communication Sciences Lausanne Switzerland

In the last decade, progress in logic synthesis has brought about new advantageous circuit representations. these representations, such as And-Inverter Graphs in the ubiquitous open-source synthesizer ABC, have inspired new designs of field programmable Gate Arrays (FPGAs), which, instead of using Look-Up Tables (LUTs), mimic the topology of the circuit representation in the basic logic cells. More recent examples are Majority-Inverter Graphs, another uniform representation which has triggered considerable interest in synthesis and which naturally suggests new logic cells. Yet, in this paper we observe how naïvely adapting technology mapping solutions for classic LUT-based FPGAs to these new architectures incurs severe shortcomings. the key issue is that LUTs are inherently input-constrained (the logic function they implement is irrelevant) and have generally a single output; on the other hand, logic cells made of uniform networks of some fundamental logic function (e.g., And-Invert) are constrained in terms of logic depth and multiple outputs are an integral feature. We introduce novel and effective solutions to address these differences; the result is a highly versatile mapper - thus enabling further research in these new architectures - with a significantly better performance than what is described in literature for one such architecture. Specifically, when we compare with the state of the art on one sample architecture, we obtain a significant decrease in area (on average 18% over several benchmarks) while also improving slightly the critical path (a reduction of 3%).

关键词： Table lookup Delays field programmable gate arrays Linear programming Libraries logic gates

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Scheduling-aware interconnect synthesis for FPGA-based Multi-Processor Systems-on-Chip

Scheduling-aware interconnect synthesis for FPGA-based Multi...

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international conference on field programmable logic and applications

作者： Edoardo Fusella Alessandro Cilardo Antonino Mazzeo Department of Electrical Engineering and Information Technologies University of Naples Federico II Napoli Italy

Multi-Processor System-on-Chip (MPSoC) applications can rely today on a very large spectrum of interconnection architectures determining various trade-offs between cost and performance. An automated methodology for optimizing FPGA-based MPSoC interconnect architectures is summarized in this poster paper. Based on the application communication requirements, the methodology concurrently defines the structure of the interconnect and the communication task scheduling, taking into account possible dependencies between tasks under given area constraints. the resulting architecture improves the level of communication parallelism while containing area and power costs.

关键词： Topology System-on-chip Schedules Integrated circuit interconnections field programmable gate arrays Bridges Parallel processing

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In-field vulnerability analysis of hardware-accelerated computer vision applications

In-field vulnerability analysis of hardware-accelerated comp...

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international conference on field programmable logic and applications

作者： I. Chadjiminas C. Kyrkou T. theocharides M. K. Michael C. Ttofis Department of Electrical and Computer Engineering KIOS Research Center for Intelligent Systems and Networks University of Cyprus Nicosia Cyprus ACC Innovations Ltd Nicosia Cyprus

In this paper, we propose an FPGA-based emulation framework that can provide dynamic vulnerability analysis for hardware-accelerated computer vision applications. the framework can be integrated alongside the targeted application, to allow for run-time, in-field, dynamically adjusted vulnerability analysis in real-world conditions, taking into consideration the non-deterministic parameters of the computer vision algorithm computations. We evaluate the proposed framework in real-time using an FPGA platform, for an obstacle avoidance (OA) computer vision application and its disparity estimation kernel to study the impact of Single-Event Upsets (SEUs).

关键词： Circuit faults Registers Computer vision Collision avoidance Kernel field programmable gate arrays Decoding

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Energy efficient partitioning of dynamic reconfigurable MRAM-FPGAs

Energy efficient partitioning of dynamic reconfigurable MRAM...

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international conference on field programmable logic and applications

作者： Ali Ahari Mojtaba Ebrahimi Mehdi B. Tahoori Karlsruhe Institute of Technology Karlsruhe Germany

Emerging non-volatile Magnetic Random Access Memory (MRAM) is a promising alternative for replacement of SRAM-based configuration bits of conventional FPGAs. However, the costs of reconfiguration in MRAM-FPGAs are typically higher than SRAM-FPGAs due to the high write latency and energy of MRAM. In this paper, a novel energy-efficient partitioning technique is proposed to minimize the number of reconfigurations and content updates for dynamic reconfigurable MRAM-FPGAs. the simulation results show that the proposed technique significantly reduces the reconfiguration energy (up to 68.1% on average) as compared to the existing partitioning techniques.

关键词： Hardware field programmable gate arrays Random access memory Magnetic tunneling MPEG 4 Standard Table lookup Resistance

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NetFPGA - rapid prototyping of high bandwidth devices in open source

NetFPGA - rapid prototyping of high bandwidth devices in ope...

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international conference on field programmable logic and applications

作者： Noa Zilberman Yury Audzevich Georgina Kalogeridou Neelakandan Manihatty Bojan Jingyun Zhang Andrew W. Moore University of Cambridge

the demand-led growth of datacenter networks has meant that many constituent technologies are beyond the budget of the wider community. In order to make and validate timely and relevant new contributions, the wider community requires accessible evaluation, experimentation and demonstration environments with specification comparable to the subsystems of the most massive datacenter networks. We demonstrate NetFPGA SUME, an open-source FPGA-based PCIe board for rapid prototyping of high bandwidth devices. NetFPGA SUME has I/O capabilities for 100Gbps operation as a networking device, computing unit, or for test and measurement.

关键词： Open source software field programmable gate arrays Random access memory Hardware Bandwidth Connectors Electronic mail

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Energy optimization of FPGA-based stream-oriented computing with power gating

Energy optimization of FPGA-based stream-oriented computing ...

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international conference on field programmable logic and applications

作者： Mohammad Hosseinabady Jose Luis Nunez-Yanez Department of Electrical and Electronic Engineering University of Bristol UK

In this paper, we propose a technique to improve the energy efficiency of FPGA devices by exploiting power gating during idle periods in streaming applications. the main idea is to shuffle idle periods during application execution so that the energy and timing overheads of turning the FPGA on and off can become acceptable. A key requirement is that fast FPGA-based accelerators are available and that the application follows a repetitive nature of execution. In this case, the accelerators work on a successive computing mode to accumulate the idle intervals in different iterations in order to make power gating feasible. Streaming on demand applications which are ubiquitous in embedded and portable devices are very good candidates to benefit from this technique. A case study is presented based on an MP3 player as the streaming application which shows up to 52.9% energy reduction.

关键词： field programmable gate arrays Energy consumption Schedules Power demand Computational modeling Delays

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First results of the silicon telescope using an 'artificial retina' for fast track finding 4

First results of the silicon telescope using an 'artificial ...

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4th international conference on Advancements in Nuclear Instrumentation Measurement Methods and their applications (ANIMMA)

作者： Neri, N. Abba, A. Bedeschi, F. Caponio, F. Cenci, R. Citterio, M. Coelli, S. Fu, J. Geraci, A. Grizzuti, M. Lusardi, N. Marino, P. Monti, M. Morello, M. J. Ninci, D. Petruzzo, M. Piucci, A. Punzi, G. Ristori, L. Spinella, F. Stracka, S. Tonalli, D. Walsh, J. INFN Sez Milano Milan Italy INFN Milano Milan Italy Politecn Milan Milan Italy INFN Pisa Pisa Italy Scuola Normale Super Pisa Pisa Italy Univ Pisa Pisa Italy CERN Geneva Switzerland Fermilab Natl Accelerator Lab Batavia IL USA

ISBN: (纸本)9781479999187

We present the first results of the prototype of a silicon tracker with trigger capabilities based on a novel approach for fast track finding. the working principle of the "artificial retina" is inspired by the processing of visual images by the brain and it is based on extensive parallelisation of data distribution and pattern recognition. the algorithm has been implemented in commercial FPGAs in three main logic modules: a switch for the routing of the detector hits, a pool of engines for the digital processing of the hits, and a block for the calculation of the track parameters. the architecture is fully pipelined and allows the reconstruction of real-time tracks with a latency less then 100 clock cycles, corresponding to 0.25 microsecond at 400 MHz clock. the silicon telescope consists of 8 layers of single-sided silicon strip detectors with 512 strips each. the detector size is about 10 cm x 10 cm and the strip pitch is 183 jam. the detectors are read out by the Beetle chip, a custom ASICs developed for LHCb, which provides the measurement of the hit position and pulse height of 128 channels. the "artificial retina" algorithm has been implemented on custom data acquisition boards based on FPGAs Xilinx Kintcx 7 1x160. the parameters of the tracks detected arc finally transferred to host PC via USB 3.0. the boards manage the read-out ASICs and the sampling of the analog channels. the read-out is performed at 40 MHz on 4 channels for each ASIC that corresponds to a decoding of the telescope information at 1.1 MHz. We report on the first results of the fast tracking device and compare with simulations.

关键词： field programmable gate arrays (FPGA)

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OpenCL computing on FPGA using multiported

OpenCL computing on FPGA using multiported

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international conference on field programmable logic and applications

作者： Shared Memory Tahsin Turker Mutlugun Sheng-De Wang National Taiwan University Taipei TW Dept of Electrical Engineering National Taiwan University Taipei 106 Taiwan

this paper focuses on memory access improvements for the OpenCL architecture for FPGAs with the goal of achieving trade-off between performance and required resources. In OpenCL compute units, there is usually a linear relation between computation time and local memory access latency. this latency is normally hidden by increasing the parallel workload. However, with such an approach, the target FPGA device could easily run out of resources. In this work, conflict-free multiported memories are used to minimize local memory access latency. Experiments show that multiported memories can successfully increase computation speed and reduce the required parallel workload for maximum throughput to practical amounts.

关键词： Random access memory Ports (Computers) field programmable gate arrays Memory management Kernel Clocks Prefetching

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Significant papers from the first 25 years of the FPL conference

Significant papers from the first 25 years of the FPL confer...

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international conference on field programmable logic and applications

作者： Philip H.W. Leong Hideharu Amano Jason Anderson Koen Bertels João M.P. Cardoso Oliver Diessel Guy Gogniat Mike Hutton JunKyu Lee Wayne Luk Patrick Lysaght Marco Platzner Viktor K. Prasanna Tero Rissa Cristina Silvano Hayden So Yu Wang The University of Sydney Australia Keio University Japan University of Toronto Canada Delft University of Technology Netherlands Universidade do Porto Portugal University of NSW Australia Universite de Bretagne-Sud Lorient FR Altera Corp San Jose CA US The University of Sydney Sydney NSW AU Imperial College London London London GB Xilinx Research Labs San Jose USA Universitat Paderborn Paderborn Nordrhein-Westfalen DE University of Southern California Los Angeles CA US Nokia Finland Politecnico di Milano Milano Lombardia IT University of Hong Kong Hong Kong HK Tsinghua University Beijing Beijing CN

the list of significant papers from the first 25 years of the field-programmable logic and applications conference (FPL) is presented in this paper. these 27 papers represent those which have most strongly influenced ... 详细信息

关键词： field programmable gate arrays Computer science Hardware Arrays Intrusion detection Design methodology

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