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Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices

Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA dev...

引用

international conference on field programmable logic and applications

作者： Mohammad Hosseinabady Jose Luis Nunez-Yanez Department of Electrical and Electronic Engineering University of Bristol UK

this paper presents a workgroup synthesis mechanism to compile an OpenCL kernel to FPGA-based accelerators embedded in a multi-core CPU system-on-a-chip (SoC). the OpenCL kernels considered in this paper exhibit regular data access patterns. Coping with the limited amount of internal memory in embedded FPGAs, the workgroup synthesis utilises a novel data access pattern formulation to describe the parallelism already provided by the OpenCL kernels. To provide an OpenCL framework prototype to validate the proposed technique, a source-to-source compiler that transforms the OpenCL kernel into C/C++ code is developed. then vendor-specific high-level synthesis tools are used to convert the C/C++ code into the FPGA bitstream. Results based on popular real applications show up to 89.8% improvement in the execution time compared to other commercial FPGA OpenCL implementations.

关键词： field programmable gate arrays Kernel Parallel processing Hardware Arrays Optimization System-on-chip

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FPGA-based all-digital software defined radio system demonstration

FPGA-based all-digital software defined radio system demonst...

引用

international conference on field programmable logic and applications

作者： Rui F. Cordeiro André Prata Arnaldo S. R. Oliveira Nuno Borges Carvalho José N. Vieira Universidade de Aveiro DETI - Instituto de Telecomuniçõacoes Universidade de Aveiro Aveiro Aveiro PT

All-digital radios allow the full digitalization of the radio system which poses an important step towards the complete software description of RF signals proposed in SDR. Using digital signal processing techniques and the integration of the radio into a single digital chip, it is expected that high flexibility in these systems will be fundamental for the next generation of wireless networks. In addition, FPGA-based architectures take advantage of the high and heterogeneous processing power of modern FPGAs as well as their dynamic configurability capabilities needed for highly flexible radio transceivers.

关键词： field programmable gate arrays Pulse width modulation Radio frequency Receivers Baseband Radio transmitters RF signals

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Pipelined NoC router architecture design with buffer configuration exploration on FPGA

Pipelined NoC router architecture design with buffer configu...

引用

international conference on field programmable logic and applications

作者： Qi Chen Qiang Liu School of Electronic Information Engineering Tianjin University China

ISBN: (纸本)9781467381239

Emerging System-on-Chip (SoC) applications on FPGAs have boosted the FPGA-based Network-on-Chip (NoC) implementations. Router microarchitecture plays a central role in the performance of an NoC. this paper investigates the router architecture in great detail and designs high throughput architecture based on the fine-grained configurability and customizability provided by FPGAs. Specifically, we 1) divide the logic operations of the router into two pipelining stages and implement a modified backpressure flow control mechanism to support high frequency and pipelined routing operation; 2) explore different buffering schemes to find an architecture which can sustain low queuing delays. the experimental results show that the pipelined architecture achieves operation clock frequency over 400 MHz, which is 3 times higher than that of an open source FPGA-based NoC, CONNECT, leading to about 5 times improvement in the network saturation throughput.

关键词： field programmable gate arrays Ports (Computers) throughput Computer architecture Pipeline processing Routing Registers

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Towards a guided design flow for heterogeneous reconfigurable architectures

Towards a guided design flow for heterogeneous reconfigurabl...

引用

international conference on field programmable logic and applications

作者： Timm Bostelmann Sergei Sawitzki FH Wedel (University of Applied Sciences) Wedel Germany

In this work we present a concept of an architecture design flow for heterogeneous reconfigurable architectures. We have a special focus on high flexibility regarding the architecture design. We cover architectures from fine-grained island-style FPGAs and heterogeneous hierarchical structures through to coarse-grained reconfigurable architectures (CGRAs). Our goal is to make the development and optimization of reconfigurable architectures more efficient and convenient. therefore our design flow includes a graphical architecture editor, which allows the user to adapt the global design structure as well as the detailed implementation of the logic blocks. An analysis tool gives the user a statistical feedback about the resource utilization of the architecture under development for a given set of benchmark applications to allow a directed exploration and optimization. We describe the envisioned design flow and compare it to a manual design flow. Finally we present the parts of the toolset that are already operational and describe how we are planning to implement the remaining tools.

关键词： field programmable gate arrays Routing Design tools Hardware design languages Optimization Benchmark testing Statistical analysis

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FPGA based nonlinear Support Vector Machine training using an ensemble learning

FPGA based nonlinear Support Vector Machine training using a...

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international conference on field programmable logic and applications

作者： Mudhar Bin Rabieah Christos-Savvas Bouganis Department of Electrical and Electronic Engineering Imperial College London

Support Vector Machines (SVMs) are powerful supervised learning methods in machine learning. However, their applicability to large problems has been limited due to the time consuming training stage whose computational cost scales quadratically with the number of examples. In this work, a complete FPGA-based system for nonlinear SVM training using ensemble learning is presented. the proposed framework builds on the FPGA architecture and utilizes a cascaded multi-precision training flow, exploits the heterogeneity within the training problem by tuning the number representation used, and supports ensemble training tuned to each internal memory structure so to address very large datasets. Its performance evaluation shows that the proposed system achieves more than an order of magnitude better results compared to state-of-the-art CPU and GPU-based implementations.

关键词： Training Support vector machines field programmable gate arrays Kernel Hardware Computer architecture Acceleration

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Optimization of an Arithmetic logic Unit using Generic Floating Point Algorithm for 12-Bit Architecture 5

Optimization of an Arithmetic Logic Unit using Generic Float...

引用

5th IEEE international conference on Control System, Computing and Engineering (ICCSCE)

作者： Anacan, Rommel M. Technol Inst Philippines Dept Elect Engn Manila Philippines

ISBN: (纸本)9781479982523

A proposed high speed generic floating point algorithm for 12-Bit Architecture is consist of adder, subtractor, multiplier, divisor, square root, and cube root modules. A novel algorithm was proposed for each modules using VHDL to optimize the speed and area as well as to attain the highest maximum operating frequency. A top down approach was applied for the modules and these were further subdivided into sub-modules for the two inputs to be combined. the novel algorithm was written in VHDL code, simulated in Xilinx 9.2i and 13.1 version and implemented in Xilinx FPGA Virtex boards. the results were analyzed and compared with different algorithms. As the FPGAs' (field programmable Gate Array) popularity increases rapidly, they are becoming more suitable in many applications that require dense computations and high frequency. the improvement in the performance of electronic systems can be traced to developments in integrated circuits which form the fundamental building blocks of modern electronics technology. As with the modern technology fast-approaching, the development of integrated circuits can also be attributed with the help of hardware description language (HDL) such as VHDL and Verilog. the need to improve the face of the ICs through the use HDL also defines the speed and area of the whole circuitry. the basis for conceptualizing the design, development, and evaluation of a generic algorithm is to provide a direct impact of improving the existing modules that was implemented on many design applications in DSP. Prior, to the development of the VHDL modules, other studies involving ALU similar to the paper were considered to determine the parameters to be observed. the enhancement of the existing VHDL modules in the other papers are implemented for the ALU and this includes the development of the new modules such as the square and cube root.

关键词： ALU Optimization Floating Point FPGA VHDL

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Mind the (synthesis) gap: Examining where academic FPGA tools lag behind industry

Mind the (synthesis) gap: Examining where academic FPGA tool...

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international conference on field programmable logic and applications

作者： Eddie Hung Department of Computing Imperial College London England

Firstly, we present VTR-to-Bitstream v2.0, the latest version of our open-source toolchain that takes Verilog input and produces a packed, placed - and now routed -solution that can be programmed onto the Xilinx commercial FPGA architecture. Secondly, we apply this updated tool to measure the gap between academic and industrial FPGA tools by examining the quality of results at each of the three main compilation stages: synthesis, packing & placement, routing. Our findings indicate that the delay gap (according to Xilinx static timing analysis) for academic tools breaks down into a 31% degradation with synthesis, 10% with packing & placement, and 15% with routing. this leads us to believe that opportunities for improvement exist not only within VPR, but also in the front-end tools that lie upstream.

关键词： Routing field programmable gate arrays Hardware design languages Video recording Table lookup Runtime Timing

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An FPGA implementation of a phylogenetic tree reconstruction algorithm using an alternative second-pass optimization

An FPGA implementation of a phylogenetic tree reconstruction...

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international conference on field programmable logic and applications

作者： Henry Block Tsutomu Maruyama Systems and Information Engineering University of Tsukuba Tsukuba JAPAN

In this paper, we present an alternative and improved FPGA hardware implementation for a phylogenetic tree reconstruction with maximum parsimony algorithm. As in our previous work, the approach is based on a particular stochastic local search algorithm that uses the Indirect Calculation of Tree Lengths method. However, now we use an alternative second-pass optimization method, for the first time, and modify the rearrangement evaluation process. As a result, we reduce the execution time by half for these two steps in the algorithm. We compare execution times against our previous hardware approach for six real-world biological datasets, obtaining an acceleration rate of around 1.2 times faster. We also show a comparison against the phylogenetic software TNT.

关键词： Phylogeny Hardware Topology field programmable gate arrays Acceleration Optimization methods

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An efficient many-core architecture for Elliptic Curve Cryptography security assessment

An efficient many-core architecture for Elliptic Curve Crypt...

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international conference on field programmable logic and applications

作者： Marco Indaco Fabio Lauri Andrea Miele Pascal Trotta Dipartimento di Automatica e Informatica Politecnico di Torino Torino Italy LACAL EPFL Lausanne Switzerland

Elliptic Curve Cryptography (ECC) is a popular tool to construct public-key crypto-systems. the security of ECC is based on the hardness of the elliptic curve discrete logarithm problem (ECDLP). Implementing and analyzing the performance of the best known methods to solve the ECDLP is useful to assess the security of ECC and choose security parameters in practice. We present a novel many-core hardware architecture implementing the parallel version of Pollard's rho algorithm to solve the ECDLP. this architecture results in a speed-up of almost 300% compared to the state of the art and we use it to estimate the monetary cost of solving the Certicom ECCp-131 challenge using FPGAs.

关键词： Pipelines field programmable gate arrays Elliptic curve cryptography Elliptic curves Table lookup Hardware

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Hybrid FPGA debug approach

Hybrid FPGA debug approach

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international conference on field programmable logic and applications

作者： Zdravko Panjkov Andreas Wasserbauer Timm Ostermann Richard Hagelauer Danube Mobile Communications Engineering Intel Mobile Communication (IMC) Linz Austria Institute for Integrated Circuits Johannes Kepler University Linz Austria

In the modern verification environment an FPGA-based prototyping has become an important part of the whole verification flow. the ability to simulate real time application in more realistic speeds allows much higher coverage than traditional HDL logic simulators. the main disadvantage of FPGA prototyping is inability to inspect and observe internal FPGA signals. Currently there are two traditional solutions for this problem. the first solution is using embedded trace-buffers to record a subset of internal signals and the second solution captures a snapshot of the current FPGA state. Both of these techniques have certain benefits and shortcomings. In this paper, we present an idea of merging these two techniques into a new hybrid approach. Using this idea we created a hybrid circuit and during our experiments showed that it preserves all good sides from both traditional approaches.

关键词： field programmable gate arrays Clocks Random access memory Digital signal processing Hardware design languages Hardware Registers

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