检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,875 篇 会议
29 篇 期刊文献
7 册 图书

馆藏范围

1,911 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,243 篇 工学
- 1,041 篇 计算机科学与技术...
- 729 篇 软件工程
- 407 篇 电气工程
- 183 篇 电子科学与技术（可...
- 74 篇 信息与通信工程
- 63 篇 控制科学与工程
- 36 篇 仪器科学与技术
- 30 篇 机械工程
- 26 篇 动力工程及工程热...
- 23 篇 建筑学
- 17 篇 土木工程
- 15 篇 核科学与技术
- 13 篇 光学工程
- 13 篇 生物工程
- 10 篇 材料科学与工程（可...
- 10 篇 生物医学工程（可授...
- 8 篇 安全科学与工程
170 篇 理学
- 101 篇 数学
- 45 篇 物理学
- 18 篇 生物学
- 16 篇 系统科学
- 9 篇 统计学（可授理学、...
- 6 篇 化学
49 篇 管理学
- 38 篇 管理科学与工程(可...
- 19 篇 工商管理
- 14 篇 图书情报与档案管...
16 篇 医学
- 14 篇 临床医学
- 12 篇 特种医学
14 篇 法学
- 12 篇 社会学
9 篇 经济学
- 9 篇 应用经济学
5 篇 农学
5 篇 军事学
2 篇 教育学

主题

833 篇 field programmab...
688 篇 field programmab...
276 篇 hardware
156 篇 computer archite...
125 篇 logic gates
112 篇 table lookup
87 篇 throughput
87 篇 clocks
83 篇 random access me...
79 篇 routing
74 篇 software
72 篇 acceleration
65 篇 delays
65 篇 optimization
62 篇 kernel
54 篇 registers
54 篇 logic
50 篇 switches
49 篇 algorithm design...
47 篇 system-on-chip

机构

14 篇 univ toronto dep...
9 篇 imperial coll lo...
8 篇 school of comput...
8 篇 department of co...
8 篇 ecole polytech f...
7 篇 univ british col...
7 篇 brigham young un...
7 篇 imperial coll lo...
7 篇 tokyo inst techn...
6 篇 univ tsukuba tsu...
6 篇 university of ch...
6 篇 department of el...
6 篇 univ warwick sch...
6 篇 xilinx inc san j...
5 篇 univ manchester ...
5 篇 department of el...
5 篇 univ toronto dep...
5 篇 inesc-id univers...
5 篇 swiss fed inst t...
5 篇 department of el...

作者

31 篇 luk wayne
21 篇 maruyama tsutomu
16 篇 koch dirk
14 篇 wayne luk
12 篇 wilton steven j....
12 篇 ienne paolo
11 篇 betz vaughn
10 篇 fahmy suhaib a.
10 篇 cheung peter y. ...
9 篇 vaughn betz
9 篇 constantinides g...
9 篇 prasanna viktor ...
9 篇 amano hideharu
8 篇 paolo ienne
8 篇 chow paul
8 篇 akash kumar
7 篇 kapre nachiket
7 篇 teich juergen
7 篇 suhaib a. fahmy
7 篇 alonso gustavo

语言

1,898 篇 英文
9 篇 其他
4 篇 中文

检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

共 1911 条记录，以下是781-790 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Reduction calculator in an FPGA based switching Hub for high performance clusters

Reduction calculator in an FPGA based switching Hub for high...

引用

international conference on field programmable logic and applications

作者： Takuya Kuhara Chiharu Tsuruta Toshihiro Hanawa Hideharu Amano Dept. of ICS Keio University Yokohama Japan The University of Tokyo Kashiwa Japan

Unused logic in the field-programmable gate array (FPGA) for the switching hub is one potential resource to accelerate the computation of data exchanged through the hub. However, for large scale scientific computation, it is difficult to implement such an accelerator on the FPGA used in high performance computers. Here, a reduction calculator for executing ARGOT (accelerated radiative transfer on grids using oct-tree) to solve the radiative transfer equation used for simulation of astronomical objects is implemented on the FPGA of PEACH2 (PCI Express Adaptive Communication Hub ver2), a low latency switching hub for high performance GPU (graphics processor unit) clusters. the implemented reduction calculator uses a pipelined tree of adders and works with a 150-MHz clock without affecting the switching hub functions. Use of the DMA (direct memory access) transfer with descriptors made it possible to improve the performance of CPU excution by a maximum of about 45 times in a real system.

关键词： Calculators field programmable gate arrays Switches Graphics processing units Ports (Computers) Adders Mathematical model

来源：评论

学校读者我要写书评

暂无评论

Characterisation of feasibility regions in FPGAs under adaptive DVFS

Characterisation of feasibility regions in FPGAs under adapt...

引用

international conference on field programmable logic and applications

作者： Nizar Dahir Pedro Campos Gianluca Tempesti Martin Trefzer Andrew Tyrrell Department of Electronics University of York

Implementing Dynamic Voltage and Frequency Scaling (DVFS) is a non-trivial task on FPGAs and requires knowledge about the feasible voltage and frequency (VF) ranges as a first step. the VF feasible ranges depend not only on the size of the critical path in the design but also on the inter- and intra-die variability on the FPGA die. Moreover, the variations in the configuration of the FPGA highly affect feasible VF ranges. therefore, it is crucial to characterise feasibility by studying the relationship between feasible VF regions and these sources of variability in FPGAs. In this paper we employ a self-checking multiplier which uses residue codes and DVFS implemented on the programmable logic component of a Xilinx Zynq ZC702 device as an error-detection circuit to study these feasible regions. Results show that, as expected, feasible VF ranges vary with FPGA configuration. More interestingly, significant variation of the feasible VF regions is found for different dies. these results highlight the necessity of dynamic self-testing as a part of an adaptive DVFS implementation on FPGAs. Employing the techniques presented in this work enables the implementation of efficient adaptive on-line DVFS on programmable logic while ensuring reliability.

关键词： field programmable gate arrays Error analysis Clocks Power demand Hardware System-on-chip Voltage control

来源：评论

学校读者我要写书评

暂无评论

A scalable FPGA architecture for nonnegative least squares problems

A scalable FPGA architecture for nonnegative least squares p...

引用

international conference on field programmable logic and applications

作者： Alric Althoff Ryan Kastner Computer Science and Engineering University of California San Diego

Nonnegative least squares (NNLS) optimization is an important algorithmic component of many problems in science and engineering, including image segmentation, spectral deconvolution, and reconstruction of compressively sensed data. Each of these areas can benefit from high performance implementations suitable for embedded applications. Unfortunately, the NNLS problem has no solution expressible in closed-form, and many popular algorithms are not amenable to compact and scalable hardware implementation. Classical iterative algorithms generally have a per-iteration computational cost with cubic growth, and interdependencies which limit parallel approaches. In this paper we develop two efficient hardware architectures. One is based on a novel algorithm we develop in this paper specifically to reduce FPGA area consumption while preserving performance. We implement our architectures on a very small FPGA and apply them to reconstruction of a compressively sensed signal showing residual error results competitive with traditional algorithms.

关键词： Hardware field programmable gate arrays Convergence Algorithm design and analysis Random access memory Computer architecture Optimization

来源：评论

学校读者我要写书评

暂无评论

Accurate power analysis for near-Vt RRAM-based FPGA

Accurate power analysis for near-Vt RRAM-based FPGA

引用

international conference on field programmable logic and applications

作者： Xifan Tang Pierre-Emmanuel Gaillardon Giovanni De Micheli École Polytechnique Fédérale de Lausanne (EPFL) Switzerland

Resistive Random Access Memory (RRAM)-based FPGA architectures employ RRAMs not only as memories to store the configuration but embed them in the datapaths of programmable routing resources to propagate signals with improved performances. Sources of power consumption have been intensively studied for conventional Static Random Access Memories (SRAM)-based FPGAs. However, very limited works focused so far on studying the power characteristics of RRAM-based FPGAs. In this paper, we first analyze the power characteristics of RRAM-based multiplexer at circuit level and then use electrical simulations to study power consumption of RRAM-based FPGA architectures. Experimental results show that RRAM-based FPGAs achieve a Power-Delay Product reduced by 50% compared to SRAM-based FPGA at nominal voltage and 20% compared to near-V t SRAM-based FPGA, respectively.

关键词： field programmable gate arrays Multiplexing Random access memory Power demand Routing Transistors Programming

来源：评论

学校读者我要写书评

暂无评论

Efficient assembly for high order unstructured FEM meshes

Efficient assembly for high order unstructured FEM meshes

引用

international conference on field programmable logic and applications

作者： Pavel Burovskiy Paul Grigoras Spencer Sherwin Wayne Luk Department of Computing Imperial College London Department of Aeronautics Imperial College London

the Finite Element Method (FEM) is a common numerical technique used for solving Partial Differential Equations (PDEs) on complex domain geometries. Large and unstructured FEM meshes are used to represent the computation domains which makes an efficient mapping of the Finite Element Method onto FPGAs particularly challenging. the focus of this paper is on assembly mapping, a key kernel of FEM, which induces the sparse and unstructured nature of the problem. We translate FEM vector assembly mapping into data access scheduling to perform vector assembly directly on the FPGA, as part of the hardware pipeline. We show how to efficiently partition the problem into dense and sparse sub-problems which map well onto FPGAs. the proposed approach, implemented on a single FPGA could outperform highly optimised FEM software running on two Xeon E5-2640 processors.

关键词： Sparse matrices Finite element analysis Assembly field programmable gate arrays Kernel Hardware Arrays

来源：评论

学校读者我要写书评

暂无评论

Compact dual block AES core on FPGA for CCM Protocol

Compact dual block AES core on FPGA for CCM Protocol

引用

international conference on field programmable logic and applications

作者： João Carlos Resende Ricardo Chaves Instituto Superior Técnico Universidade de Lisboa/INESC-ID Lisbon Portugal

this paper presents a compact and FPGA based implementation of the AES encryption standard, specifically designed for processing two independent 128-bit input blocks in feedback modes. this configuration is particularly focused on the Counter with CBC-MAC Protocol, but can also be adapted to other AES based encryption-authentication protocols requiring the processing of two independent data streams. Most of the state of the art solutions implementing CCMP consider large datapaths, sometimes with separated encryption datapaths for the different data streams, leading to low resource efficiency. the work herein proposed suggests that with adequate FPGA component usage and with proper data scheduling a very compact and efficient dual AES core can be derived particularly on FPGAs. Overall, the proposed structure allows for a throughput of 1.7Gbps while achieving a throughput/Slice efficiency of 24.22 Mbps/Slice, 47% higher than the existing related state of the art.

关键词： Radiation detectors field programmable gate arrays Encryption Shift registers Protocols throughput

来源：评论

学校读者我要写书评

暂无评论

Towards heterogeneous solvers for large-scale linear systems

Towards heterogeneous solvers for large-scale linear systems

引用

international conference on field programmable logic and applications

作者： Stylianos I. Venieris Grigorios Mingas Christos-Savvas Bouganis Department of Electrical and Electronic Engineering Imperial College London London UK

Applying Linear Regression to systems with a massive amount of observations, a scenario which is becoming increasingly common in the era of Big Data, poses major algorithmic and computational challenges. this paper proposes a novel high-performance FPGA-based architecture for large-scale Linear Regression problems as well as a heterogeneous system comprising the custom FPGA architecture, an enhanced GPU module and a multi-core CPU for addressing the aforementioned problem. the system adaptively assigns Linear Regression workloads to the three computing devices to minimise runtime. the device with the highest performance is chosen based on an analytical framework, as well as the workload's size and structure. A quantitative comparison with existing FPGA, GPU and multi-core CPU designs yields speed-ups of up to 18.07×, 32.67× and 25.84× respectively.

关键词： Graphics processing units field programmable gate arrays Computer architecture Digital signal processing Matrix decomposition Performance evaluation Algorithm design and analysis

来源：评论

学校读者我要写书评

暂无评论

UniStream: A unified stream architecture combining configuration and data processing

UniStream: A unified stream architecture combining configura...

引用

international conference on field programmable logic and applications

作者： Jian Yan Jifang Jin Ying Wang Xuegong Zhou Philip Leong Lingli Wang State Key Laboratory of ASIC and System Fudan University Shanghai China School of Electrical and Information Engineering The University of Sydney Australia

this paper proposes UniStream, a unified stream architecture based on point-to-point stream channels combining both bitstream configuration and data stream processing. In addition, unified APIs are provided to support bitstream configuration and data stream processing, as well as the stream interconnect. A cost model is also presented for the overhead on the stream interconnect, hardware task configuration and data stream processing at system level, which can be used during the early stage of development. the flexibility and high efficiency of UniStream are demonstrated on Xilinx Virtex-5 and Virtex-6 FPGAs. Experimental results on bitstream configuration/ read-back, data encryption/decryption and Discrete Cosine Transformation show that performance can be significantly improved with different stream modes.

关键词： Hardware Computer architecture field programmable gate arrays System-on-chip throughput Software Data models

来源：评论

学校读者我要写书评

暂无评论

Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow

Synthesizable FPGA fabrics targetable by the Verilog-to-Rout...

引用

international conference on field programmable logic and applications

作者： Jin Hee Kim Jason H. Anderson Dept. of Electrical and Computer Engineering University of Toronto Toronto ON Canada

We consider implementing FPGAs using a standard cell design methodology, and present a framework for the automated generation of synthesizable FPGA fabrics. the open-source Verilog-to-Routing (VTR) FPGA architecture evaluation framework [1] is extended to generate synthesizable Verilog for its in-memory FPGA architectural device model. the Verilog can be synthesized into standard cells, placed and routed using an ASIC design flow. A second extension to VTR generates a configuration bitstream for the FPGA; that is, the bitstream configures the FPGA to realize a user-provided placed and routed design. the proposed framework and methodology opens the door to silicon implementation of a wide range of VTR-modelled FPGA fabrics. In an experimental study, area and timing-optimized FPGA implementations in 65nm TSMC standard cells are compared with a 65nm Altera commercial FPGA.

关键词： field programmable gate arrays Microprocessors Routing Video recording Hardware design languages Table lookup

来源：评论

学校读者我要写书评

暂无评论

CoRAM++: Supporting data-structure-specific memory interfaces for FPGA computing

CoRAM++: Supporting data-structure-specific memory interface...

引用

international conference on field programmable logic and applications

作者： Gabriel Weisz James C. Hoe Carnegie Mellon University Pittsburgh PA USA

Facilitating DRAM access is an essential part of an application programming environment for FPGA computing. Existing FPGA application programming environments primarily focus on support for simple, regular memory access patterns, such as block copy and streaming. this paper presents CoRAM++, a programming environment for FPGA computing that is based on an extensible set of data-structure-specific memory interfaces. CoRAM++ supports complex data structures, such as multidimensional arrays and linked lists, in addition to simple data access patterns. CoRAM++ defines an appropriate application-level interface for each supported data structure, and provides a specialized soft-logic implementation of the supporting datapath to memory. We evaluated the effectiveness of the CoRAM++ data-structure-specific approach in three application scenarios based on streams, multi-dimensional arrays and linked lists. Our results show that the CoRAM++ programming environment can offer convenient application-level interfaces without penalizing DRAM access performance.

关键词： Hardware Random access memory Kernel field programmable gate arrays Message systems Ports (Computers) Arrays

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共192页 << < 75 76 77 78 79 80 81 82 83 84 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：