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检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

共 1908 条记录，以下是71-80 订阅

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NOVEL FPGA BASED HAAR CLASSIFIER FACE DETECTION ALGORIthM ACCELERATION

NOVEL FPGA BASED HAAR CLASSIFIER FACE DETECTION ALGORITHM AC...

引用

18th international conference on field programmable and logic applications

作者： Gao, Changjian Lu, Shih-Lien Broadcom Corp Wireless Connect 16340 W Bernardo Dr San Diego CA 92127 USA Intel Corp Microarchitecture Res Hillsboro OR 97124 USA

ISBN: (纸本)9781424419609

We present here a novel approach to use FPGA to accelerate the Haar-classifier based face detection algorithm. With highly pipelined microarchitecture and utilizing abundant parallel arithmetic units in the FPGA, we've achieved real-time performance of face detection having very high detection rate and low false positives. Moreover, our approach is flexible toward the resources available on the FPGA chip. this work also provides us an understanding toward using FPGA for implementing non-systolic based vision algorithm acceleration. Our implementation is realized on a HiTech Global PCIe card that contains a Xilinx XC5 VLX110T FPGA chip.

关键词： field programmable gate arrays (FPGA)

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An Embedded Dynamically Self-Reconfigurable Master-Slaves MPSoC Architecture

An Embedded Dynamically Self-Reconfigurable Master-Slaves MP...

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18th international conference on field programmable and logic applications

作者： Karras, Kimon Manolakos, Elias S. Univ Athens Dept Informat & Telecommun GR-10679 Athens Greece

ISBN: (纸本)9781424419609

A dynamically sefl-reconfigurable Master-Slaves MPSoC architecture framework is introduced which can be fully embedded into a single FPGA device. the Master core can request a Configuration Manager module to add, or remove, a slave core at runtime. If the request can be satisfied, self-reconfiguration commences, implemented by a pipeline of light-weight specialized blocks. the M-S architecture utilizes a simple and general token-based bus control mechanism that is reconfiguration aware. All system modules have been described in synthesizable VHDL. A first system prototype has been built and validated using the affordable XUP XC2VP30 board. Even when using CRC check of bitstreams dynamic reconfiguration can proceed at the maximum speed that can be supported by the ICAP Xilinx interface. the reconfiguration support logic consumes as little as 1012 slices on the Virtex II Pro FPGA.

关键词： field programmable gate arrays (FPGA)

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COMPILER GENERATED SYSTOLIC ARRAYS FOR WAVEFRONT ALGORIthM ACCELERATION ON FPGAS

COMPILER GENERATED SYSTOLIC ARRAYS FOR WAVEFRONT ALGORITHM A...

引用

18th international conference on field programmable and logic applications

作者： Buyukkurt, Betul Najjar, Walid A. Sandbridge Technol Inc Tarrytown NY 10591 USA Univ Calif Riverside Dept Comp & Engn Riverside CA 92521 USA

ISBN: (纸本)9781424419609

Wavefront algorithms, such as the Smith-Waterman algorithm, are commonly used in bioinformatics for exact local and global sequence alignment. these algorithms are highly computationally intensive and are therefore excellent candidates for FPGA-based code acceleration. However there is no standard form of these algorithms, they are used in a wide variety of situations with various constraints. It is therefore not practical to have a standard kernel that can be mapped to an FPGA, hence the importance of being able to compile such codes from a high level language. ROCCC is a C to VHDL compiler, which optimizes and parallelizes the most frequently executed kernel loops in applications such as in multimedia, scientific and high-performance computing. In this paper we describe the transformations performed by ROCCC, which transformed the kernel of the Smith-Waterman algorithm into a hardware systolic array that is mapped onto the FPGA on the SGI Altix RASC blade. We report a throughput increase by over 3,000X over a 2.8 GHz Xeon.

关键词： field programmable gate arrays (FPGA)

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GICS: GENERIC INTERCONNECTION SYSTEM

GICS: GENERIC INTERCONNECTION SYSTEM

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18th international conference on field programmable and logic applications

作者： Malek, Tomas Martinek, Tomas Korenek, Jan CESNET Zspo Zikova 4 Prague 16000 Czech Republic Brno Univ Technol Fac Informat Technol Brno 61266 Czech Republic

ISBN: (纸本)9781424419609

the division of an application between a conventional processor and an acceleration card with FPGA chips has been proved as a suitable way for an acceleration of computationally intensive tasks. In such applications, the designer usually has to implement an interconnection between components placed in FPGA and the host system bus. this task is often complicated by different requirements of user components for throughput, latency of reading operations, need for DMA transfers etc. the objective of this work is to show a new approach for implementation of interconnection systems and to enable the designer to focus on the development of the target application. the proposed interconnection system is based on tree topology. the system eliminates the sensitivity of wide buses to the distance, supports the connection of components with different requirements for throughput, supports split transaction model and many other features. the proposed system is implemented and evaluated on chips with Virtex 5 technology.

关键词： field programmable gate arrays (FPGA)

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CLUSTER ARCHITECTURE BASED ON LOW COST RECONFIGURABLE HARDWARE

CLUSTER ARCHITECTURE BASED ON LOW COST RECONFIGURABLE HARDWA...

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18th international conference on field programmable and logic applications

作者： Pedraza, Cesar Castillo, Emilio Castillo, Javier Camarero, Cristobal Bosque, Jose L. Martinez, Jose I. Menendez, Rafael Univ Rey Juan Carlos Escuela Tecn Super Ingn Informat Madrid Spain Univ Cantabria Dept Elect Comp Santander Spain

ISBN: (纸本)9781424419609

the SMILE project accelerates scientific and industrial applications by means of a cluster of low-cost FPGA boards. With this approach the intensive calculation tasks are accelerated using the FPGA logic, while the communication patterns of the applications remains unchanged by using a Message Passing Library over Linux. this paper explains the cluster architecture: the SMILE nodes and the developed high-speed communication network for the FPGA RocketIO interfaces. A SystemC model developed to simulate the cluster is also detailed. In order to show the potential of the SMILE proposal a Content-Based Information Retrieval parallel application has been developed and compared with a HP cluster architecture in terms of response time and power consumption.

关键词： field programmable gate arrays (FPGA)

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FPGA ACCELERATION OF MONTE-CARLO BASED CREDIT DERIVATIVE PRICING

FPGA ACCELERATION OF MONTE-CARLO BASED CREDIT DERIVATIVE PRI...

引用

18th international conference on field programmable and logic applications

作者： Kaganov, Alexander Chow, Paul Lakhany, Asif Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada Quantitat Res Algorithm Incorp Toronto ON M5T 2C6 Canada

ISBN: (纸本)9781424419609

In recent years the financial world has seen an increasing demand for faster risk simulations, driven by growth in client portfolios. Traditionally many financial models employ Monte-Carlo simulation, which can take excessively long to compute in software. this paper describes a hardware implementation for Collateralized Debt Obligations (CDOs) pricing, using the One-Factor Gaussian Copula (OFGC) model. We explore the precision requirements and the resulting resource utilization for each number representation. Our results show that our hardware implementation mapped onto a Xilinx XC5VSX50T is over 63 times faster than a software implementation running on a 3.4 GHz Intel Xeon processor.

关键词： field programmable gate arrays (FPGA)

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A VARIATION-AWARE CONSTANT-ORDER OPTIMIZATION SCHEME UTILIZING DELAY DETECTORS TO SEARCH FOR FASTEST PAthS ON FPGAS

A VARIATION-AWARE CONSTANT-ORDER OPTIMIZATION SCHEME UTILIZI...

引用

18th international conference on field programmable and logic applications

作者： Kobayashi, K. Kume, Y. Ngo, C. L. Sugihara, Y. Onodera, H. Kyoto Univ Dept Commun & Comp Engn Grad Sch Informat Sakyo Ku Kyoto 6068501 Japan

ISBN: (纸本)9781424419609

We propose a variation-aware post-fabrication optimization scheme on FPGAs. Variation-aware optimization usually takes huge measurement cost. the proposed scheme achieves a constant optimization cost for any circuit configuration. We utilize delay detectors embedded in clustered CLBs to choose fastest paths among multiple candidates. the delay detectors enable simultaneous measurement of critical path candidates to partition all critical paths into segments. the number of measurement to choose fastest paths on all critical paths does not depends on configurations but on FPGA architectures. We confirm that a simple heuristic algorithm can find the order of measurement near the lowest bound of the measurement cost and it is almost constant regardless of circuit configurations.

关键词： field programmable gate arrays (FPGA)

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COMBINING DATA REUSE EXPLOITATION WIth DATA-LEVEL PARALLELIZATION FOR FPGA TARGETED HARDWARE COMPILATION: A GEOMETRIC PROGRAMMING FRAMEWORK

COMBINING DATA REUSE EXPLOITATION WITH DATA-LEVEL PARALLELIZ...

引用

18th international conference on field programmable and logic applications

作者： Liu, Qiang Constantinides, George A. Masselos, Konstantinos Cheung, Peter Y. K. Imperial Coll London London SW7 2BT England Univ Peloponnese Tripoli 22100 Greece

ISBN: (纸本)9781424419609

A geometric programming framework is proposed in this paper to automate exploration of the design space consisting of data reuse (buffering) exploitation and loop-level parallelization, in the context of FPGA-targeted hardware compilation. We expose the dependence between data reuse and data-level parallelization and explore both problems under the on-chip memory constraint for performance-optimal designs within a single optimization step. Results from applying this framework to several real benchmarks demonstrate that given different constraints on on-chip memory utilization, the corresponding performance-optimal designs are automatically determined by the framework, and performance improvements up to 4.7 times have been achieved compared with the method that first explores data reuse and then performs parallelization.

关键词： field programmable gate arrays (FPGA)

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SECURE FPGA CONFIGURATION ARCHITECTURE PREVENTING SYSTEM DOWNGRADE

SECURE FPGA CONFIGURATION ARCHITECTURE PREVENTING SYSTEM DOW...

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18th international conference on field programmable and logic applications

作者： Badrignans, Benoit Elbaz, Reouven Torres, Lionel Univ Montpellier 2 CNRS LIRMM UMR C5506 Montpellier France SAS NETHEOS Montpellier France Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

ISBN: (纸本)9781424419609

In the context of FPGAs, system downgrade consists in preventing the update of the hardware configuration or in replaying an old bitstream. the objective can be to preclude a system designer from fixing security vulnerabilities in a design. Such an attack can be performed over a network when the FPGA-based system is remotely updated or on the bus between the configuration memory and the FPGA chip at power-up. Several security schemes providing encryption and integrity checking of the bitstream have been proposed in the literature. However, as we show in this paper, they do not detect the replay of old FPGA configurations;hence they provide adversaries with the opportunity to downgrade the system. We thus propose a new architecture that, in addition to ensuring bitstream confidentiality and integrity, precludes replay of old bitstreams. We show that the hardware cost of this architecture is negligible.

关键词： field programmable gate arrays (FPGA)

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FPGA IMPLEMENTATION OF A FLEXIBLE DECODER FOR LONG LDPC CODES

FPGA IMPLEMENTATION OF A FLEXIBLE DECODER FOR LONG LDPC CODE...

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18th international conference on field programmable and logic applications

作者： Beuschel, Christiane Pfleiderer, Hans-Joerg Univ Ulm Inst Microelect D-89081 Ulm Germany

ISBN: (纸本)9781424419609

Over the last years LDPC codes became more and more popular because of their near Shannon limit error correcting performance. Structured code classes which ease decoder design have already been standardized for DVB-S2, IEEE WiMax 802.16e or WiFi. In this paper we introduce a flexible decoder architecture which can decode any structured or unstructured LDPC code using the identical hardware. Furthermore we present a mapping algorithm which "compiles" the parity-check matrix of the desired LDPC code. this concept allows adaption of the decoder controller to different LDPC codes without requiring a new synthesis run. We implemented the proposed decoder on a XILINX XC4LX160 FPGA and give bit error rates to verify design and mapping algorithm. In contrast to previously presented flexible implementations our design is able to decode LDPC codes of 30 times longer codeword lengths up to N = 65, 000.

关键词： field programmable gate arrays (FPGA)

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