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Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference

Fast hierarchical implementation of sequential tree-reweight...

引用

international conference on field programmable logic and applications

作者： Skand Hurkat Jungwook Choi Eriko Nurvitadhi José F. Martínez Rob A. Rutenbar Computer Systems Laboratory Cornell University Ithaca NY USA Dept. of Electrical and Computer Engineering Intel Labs Hillsboro OR USA Dept. of Computer Science University of Illinois at Urbana-Champaign Urbana IL USA

Maximum a posteriori probability (MAP) inference on Markov random fields (MRF) is the basis of many computer vision applications. Sequential tree-reweighted belief propagation (TRW-S) has been shown to provide very good inference quality and strong convergence properties. However, software TRW-S solvers are slow due to the algorithm's high computational requirements. A state-of-the-art FPGA implementation has been developed recently, which delivers substantial speedup over software. In this paper, we improve upon the TRW-S algorithm by using a multi-level hierarchical MRF formulation. We demonstrate the benefits of Hierarchical-TRW-S over TRW-S, and incorporate the proposed improvements on a Convey HC-1 CPU-FPGA hybrid platform. Results using four Middlebury stereo vision benchmarks show a 21% to 53% reduction in inference time compared with the state-of-the-art TRW-S FPGA implementation. To the best of our knowledge, this is the fastest hardware implementation of TRW-S reported so far.

关键词： Convergence Benchmark testing Belief propagation Hardware Software algorithms field programmable gate arrays Inference algorithms

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Limits of FPGA acceleration of 3D Green's Function computation for geophysical applications

Limits of FPGA acceleration of 3D Green's Function computati...

引用

international conference on field programmable logic and applications

作者： Nachiket Kapre Jayakrishnan Selva Kumar Parjanya Gupta Sagar Masuti Sylvain Barbot School of Computer Engineering Nanyang Technological University Singapore Earth Observatory of Singapore Nanyang Technological University Singapore

FPGA-based accelerators can outperform multi-core, GPU and Xeon Phi based platforms by at as much as 2.8× for 3D Green's Function processing in geophysics while delivering superior energy efficiency. FPGAs can efficiently implement a complex mixture of compute patterns that include data-parallelism, reductions, dataflow and streaming computations using spatial parallelism to deliver these speedups and power benefits. Since 3D Green's Function is highly-parallel but communication bound, we optimize the FPGA implementation by considering loop restructuring and tiling optimizations to minimize and regularize off-chip accesses. Furthermore, we configure the FPGA to implement the key compute intensive kernels at double-precision as well as single-precision to exploit the uncertainty in measurements of earthquake monitoring sensors. For 512×512×512 problem size, the Xilinx SX475T (Maxeler MAX3) outperforms the fastest architecture by 1.1-1.4× (double-precision), 2.2-2.8× (single-precision) with 1.2× better energy efficiency.

关键词： field programmable gate arrays Green's function methods Graphics processing units three-dimensional displays Kernel Mathematical model Random access memory

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SysAlloc: A hardware manager for dynamic memory allocation in heterogeneous systems

SysAlloc: A hardware manager for dynamic memory allocation i...

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international conference on field programmable logic and applications

作者： Zeping Xue David B. thomas Department of Electrical and Electronic Engineering Imperial College London London UK

System-on-chip designs are increasingly complex and dynamic, with many IP cores, CPUs and off-chip Memories interconnected via shared buses. Static allocation of RAM resources requires designers to analyse the memory needs of each component, which can lead to poor memory efficiency, and is infeasible in a dynamically changing system. Dynamic memory allocation is one solution to this problem, but is usually only supported in software. We propose SysAlloc, a hardware-based dynamic memory allocation scheme for heterogeneous systems, which allows software and hardware to access a shared memory allocator, and allows dynamic memory allocation in the absence of software. Our allocation protocol is accessible to any client which can perform memory reads and writes over a shared bus, including software, RTL, and HLS clients, and can scale at run-time to any number of active clients. In contrast to existing designs, the proposed allocator can manage DDR-scale memories while having constant FPGA resource utilisation. We evaluate SysAlloc's protocol and memory manager in a Zynq system with both software and hardware clients, demonstrating scaling to 15 concurrent clients, and a peak system allocation rate of 1.36 million allocations/second when managing 128MB of DDR for 4 clients.

关键词： Resource management Hardware Memory management Random access memory Software field programmable gate arrays System-on-chip

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Serial and parallel interleaved modular multipliers on FPGA platform

Serial and parallel interleaved modular multipliers on FPGA ...

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international conference on field programmable logic and applications

作者： Khalid Javeed Xiaojun Wang Mike Scott School of Electronics Engineering Dublin City University Dublin Ireland CertiVox UK United Kingdom

Modular multiplication is a core operation in all public key based cryptosystems. the performance of these cryptosystems can be enhanced substantially by incorporating an optimized modular multiplier. this paper presents serial and parallel radix-4 modular multipliers based on interleaved multiplication algorithm and Montgomery power laddering technique. A serial radix-4 interleaved modular multiplier provides 50% reduction in the required clock cycles. In addition to the reduction in clock cycles, a parallel modular multiplier maintains a critical path delay comparable to the bit serial interleaved multipliers. the proposed designs are implemented in Verilog HDL and synthesized targeting virtex-6 FPGA platform using Xilinx ISE 14.2 Design suite. the serial radix-4 multiplier computes a 256-bit modular multiplication in 1.3μs, occupies 3.9K LUTs, and runs at 96 MHz. the parallel radix-4 multiplier takes 0.77μs, occupies 5.3K LUTs, and runs at 166 MHz. the results show that the parallel radix-4 modular multiplier provides 62% and 49% speed-up over the corresponding bit serial and bit parallel versions, respectively. thus, these designs are suitable to accelerate modular multiplication in many cryptographic processors.

关键词： field programmable gate arrays Adders Clocks Hardware Elliptic curve cryptography Table lookup Multiplexing

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High speed ECC implementation on FPGA over GF(2m)

High speed ECC implementation on FPGA over GF(2m)

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international conference on field programmable logic and applications

作者： Zia U. A. Khan Mohammed Benaissa Department of Electronic and Electrical Engineering University of Sheffield Sheffield UK

High speed Elliptic Curve Cryptography (ECC) implementations on field programmable Gate Array (FPGA) are highly desirable for applications requiring high speed cost effective and flexible implementations of public key cryptography. Recently, many binary ECC hardware accelerators have been presented based on the Montgomery point multiplication by exploiting the underlying parallelism of the point multiplication (PM). In this paper, we present a combined Montgomery point multiplication algorithm to achieve low latency ECC point multiplication by using novel pipelined full precision parallel multipliers over GF(2 m ). We adopt a careful schedule of point operations to achieve low latency and a smart pipelining in the ECC architecture to reduce the critical path delay. Our proposed ECC architecture is implemented on Virtex5 (XCV5LX110) for a fair comparison and on Virtex7 (XC7VX550T) to quantify performance. Our Virtex5 based implementation over GF(2 163 ), consumes 10363 slices, takes only 5.1 μs for an ECC point multiplication with a frequency of 153 MHz, and has a latency of 780 clock cycles. Our Virtex-5 performance outperforms the fastest reported work on the same platform. Our Virtex7 implementation which can compute an ECC PM in 3.50 μs at a frequency of 223 MHz while utilising only 8736 slices is the highest speed implementation reported to date on FPGA.

关键词： Clocks Pipeline processing Delays Elliptic curve cryptography field programmable gate arrays Computer architecture Registers

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Temperature-triggered behavioral IPs HW Trojan detection method with FPGAs

Temperature-triggered behavioral IPs HW Trojan detection met...

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international conference on field programmable logic and applications

作者： Xiaotong Li Benjamin Carrion Schafer Department of Electronic and Information Engineering The Hong Kong Polytechnic University

this works targets the detection of temperature triggered HW Trojans, in particular for third party behavioral IPs (3PBIPs) given in ANSI-C. One of the biggest advantages of C-Based VLSI design is its ability to automatically generate architectures with different trade-offs by only setting different synthesis options. this work uses this property to detect temperature-triggered HW Trojan. A complete design flow is presented. It comprises two main phases: (1) In the first phase, a design space explorer generates micro-architectures with different area vs. power trade-offs automatically for the given behavioral IP. (2) the second phase, maps three of these micro-architectures with different power profiles onto a reconfigurable computing board to create a 3-way redundant system. this system combined with a majority voter scheme is used to detect if a HW Trojan is present in the behavioral IP. Having different power profiles implies that each micro-architecture has a different thermal behavior and thus will trigger the HW Trojan at different time intervals. the outputs of the three designs are compared for discrepancies at regular intervals, allowing our method to therefore exactly pinpoint the exact trigger temperature of the HW Trojan. A case study is presented showing the effectiveness of our method.

关键词： Trojan horses field programmable gate arrays Temperature measurement Temperature sensors Hardware

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Scavenger: Automating the construction of application-optimized memory hierarchies

Scavenger: Automating the construction of application-optimi...

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international conference on field programmable logic and applications

作者： Hsin-Jung Yang Kermin Fleming Michael Adler Felix Winterstein Joel Emer CSAIL Massachusetts Institute of Technology SSG Intel Corporation Ground Station Systems Division European Space Agency NVIDIA Research

High-level abstractions separate algorithm design from platform implementation, allowing programmers to focus on algorithms while building increasingly complex systems. this separation also provides system programmers and compilers an opportunity to optimize platform services for each application. In FPGAs, this platform-level malleability extends to the memory system: unlike general-purpose processors, in which memory hardware is fixed at design time, the capacity, associativity, and topology of FPGA memory systems may all be tuned to improve application performance. Since application kernels often use few memory resources, substantial memory capacity may be available to the platform for use on behalf of the user program. In this work, we perform an initial exploration of methods for automating the construction of these application-specific memory hierarchies. Although exploiting spare resources can be beneficial, naïvely consuming all memory resources may cause frequency degradation. To relieve timing pressure in large BRAM structures, we provide microarchitectural techniques to trade memory latency for design frequency. We demonstrate, by examining both hand-assembled and HLS-compiled benchmarks, that our application-optimized memory system can improve pre-existing application runtime by 25% on average.

关键词： field programmable gate arrays Program processors System-on-chip Microarchitecture Memory management Random access memory Kernel

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An automated technique to generate relocatable partial bitstreams for Xilinx FPGAs

An automated technique to generate relocatable partial bitst...

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international conference on field programmable logic and applications

作者： Roel Oomen Tuan Nguyen Akash Kumar Henk Corporaal State Key Laboratory of Fluid Power Transmission and Control Zhejiang University Hangzhou China Woodruff School of Mechanical Engineering Huazhong University of Science and Technology Wuhan GA China

Partial reconfiguration is a technique used to increase the flexibility of an FPGA-based system by reprogramming parts of the system dynamically without interrupting the operation of the other modules. Despite the runtime benefits offered by partially reconfigurable (PR) systems, creating and storing partial bitstreams (PBs) are becoming major concerns for system architects when the numbers of reconfigurable partitions (RPs) and PR modules (PRMs) increase. It takes significant amount of time to generate the PBs for PR systems with large number of RPs and PRMs. More importantly, when the mapping relationship between PRMs and RPs is many-to-many, several almost-identical PBs of one PRM must be stored separately which leads to inefficient utilization of the memory storage. therefore, bitstream relocation is drawing interests from the research community as a viable solution. Yet almost none of the works are able to demonstrate a coherent method to not only create relocatable PBs for complex and large PRMs in variable-size RPs but also how to do that automatically to free the designer from the tedious and error prone manual processes. In this paper, we propose a new technique to fill that gap. the method is successfully developed for Xilinx Virtex 7 devices using Vivado design tool flow.

关键词： field programmable gate arrays Table lookup Routing Timing Pins Runtime Algorithm design and analysis

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A resilient, flash-free soft error mitigation concept for the CBM-ToF read-out chain via GBT-SCA

A resilient, flash-free soft error mitigation concept for th...

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international conference on field programmable logic and applications

作者： Andrei-Dumitru Oancea Christian Stuellein Jano Gebelein Udo Kebschull University of Frankfurt Frankfurt Germany

the ToF detector read-out chain of the upcoming CBM experiment at FAIR will be equipped with FPGA-based read-out boards (ROBs), which are going to be operated in a radiation environment. Flash-based FPGAs are not an option for this experiment due to their low total ionizing dose limit compared to SRAM-based FPGAs, and therefore the latter is foreseen for the ROBs. Consequently, precautions against soft errors in the configuration memories of the FPGAs need to be taken to keep the chain operational. the proposed approach merges on-chip single upset correction with external intervention for multiple-bit upsets and resets. the external intervention is going to be implemented via the control path of the chain through the GBT-SCA, which offers a JTAG interface, as well as interrupt-capable GPIOs among other features. thus, the use of the GBT-SCA enables an event-driven configuration upset mitigation concept, while being itself radiation hardened by design. Conventional blind configuration scrubbing would cause a continuous load on the control path, while the selective frame scrubbing reduces this load significantly. the concept has been validated in beamtests conducted at COSY, FZ Juelich, Germany. the concept, the beamtest results and limitations of the implementation are presented and discussed in this paper.

关键词： IP networks field programmable gate arrays Data acquisition Protons Equalizers Monitoring Maintenance engineering

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Hybrid breadth-first search on a single-chip FPGA-CPU heterogeneous platform

Hybrid breadth-first search on a single-chip FPGA-CPU hetero...

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international conference on field programmable logic and applications

作者： Yaman Umuroglu Donn Morrison Magnus Jahre Department of Computer and Information Science Norwegian University of Science and Technology Trondheim Norway

Large and sparse small-world graphs are ubiquitous across many scientific domains from bioinformatics to computer science. As these graphs grow in scale, traversal algorithms such as breadth-first search (BFS), fundamental to many graph processing applications and metrics, become more costly to compute. the cause is attributed to poor temporal and spatial locality due to the inherently irregular memory access patterns of these algorithms. A large body of research has targeted accelerating and parallelizing BFS on a variety of computing platforms, including hybrid CPU-GPU approaches for exploiting the small-world property. In the same spirit, we show how a single-die FPGA-CPU heterogeneous device can be used to leverage the varying degree of parallelism in small-world graphs. Additionally, we demonstrate how dense rather than sparse treatment of the BFS frontier vector yields simpler memory access patterns for BFS, trading redundant computation for DRAM bandwidth utilization and faster graph exploration. On a range of synthetic small-world graphs, our hybrid approach performs 7.8× better than software-only and 2× better than accelerator-only implementations. We achieve an average traversal speed of 172 MTEPS (millions of traversed edges per second) on the ZedBoard platform, which is more than twice as effective as the best previously published FPGA BFS implementation in terms of traversals per bandwidth.

关键词： Random access memory field programmable gate arrays Bandwidth Switches Sparse matrices Parallel processing Arrays

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