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检索条件"任意字段=18th International Conference on Field Programmable and Logic Applications"

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Using an OpenCL framework to evaluate interconnect implementations on FPGAs 24

Using an OpenCL framework to evaluate interconnect implement...

引用

24th international conference on field programmable logic and applications, FPL 2014

作者： Mirian, Vincent Chow, Paul Department of Computer and Electrical Engineering University of Toronto Toronto Canada

ISBN: (纸本)9783000446450

field programmable Gate Arrays (FPGAs) are an ideal platform for building systems with custom hardware accelerators, however managing these systems is still a major challenge. the OpenCL standard has become accepted as a good programming model for managing heterogeneous platforms due to its rich constructs. Although commercial OpenCL frameworks are now emerging, there is a need for an open-source OpenCL framework that facilitates the exploration of the overall system architecture and software, as well as the implementation and architectures of the custom hardware accelerators (devices). In this paper, we use an OpenCL framework to compare interconnect implementations for a simple multiprocessor accelerator. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Fast and accurate SEU-tolerance characterization method for Zynq SoCs 24

Fast and accurate SEU-tolerance characterization method for ...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Villata, Igor Bidarte, Unai Kretzschmar, Uli Astarloa, Armando Lazaro, Jesus Department of Electronics and Telecommunications University of the Basque Country UPV/EHU Bilbao Spain

ISBN: (纸本)9783000446450

In this paper a new SEU (Single Event Upset) emulation method for testing fault tolerant systems in FPGAs is presented. It is implemented on a 'Xilinx Zynq®-7000 All programmable System on Chip (SoC)' device, which combines a hard microprocessor with programmable logic. An important new feature is that an internal hardware configuration interface controlled by this microprocessor is provided. this interface is used for injecting faults into the configuration bitstream in order to emulate radiation effects. Since both the processing system and the programmable logic are in the same chip, this method has the high speed characteristics of internal fault injection methods. As a hard internal configuration interface is provided, a configuration bit belonging to the internal interface port cannot be flipped and injection side effects are avoided. this method is especially suitable for testing complex real fault-tolerant FPGA designs because no substantial modifications need to be added to the original design. A universal verification system is proposed to avoid designing complex external application-dependent testbenches. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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A design support tool set for asynchronous circuits with bundled-data implementation on FPGAs 24

A design support tool set for asynchronous circuits with bun...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Takizawa, Keitaro Hosaka, Shunya Saito, Hiroshi University of Aizu 965-8580 Japan

ISBN: (纸本)9783000446450

In this paper, we propose a design support tool set for asynchronous circuits with bundled-data implementation to implement them on commercial FPGAs easily considering a latency constraint. the design support tool set consists of six tools to automate constraint generation, timing verification, and delay adjustment for bundled-data implementation. In the experiments, we synthesize two circuits using the proposed tool set and compare area, performance, power consumption, and energy consumption with the synchronous counterparts. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Source-level debugging for FPGA high-level synthesis 24

Source-level debugging for FPGA high-level synthesis

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24th international conference on field programmable logic and applications, FPL 2014

作者： Calagar, Nazanin Brown, Stephen D. Anderson, Jason H. Dept. of Electrical and Computer Engineering University of Toronto TorontoON Canada

ISBN: (纸本)9783000446450

We describe a source-level debugging framework for FPGA high-level synthesis (HLS) that offers gdb-like step, break, and data inspection functionality for an HLS-generated hardware circuit. With the proposed framework, the user can inspect the values of logic signals in the hardware from the C source code perspective. the logic signal values come from one of two sources: 1) a logic simulation of the RTL, or 2) an actual execution of the hardware on an FPGA. In addition to the software-like ecosystem for FPGA HLS debugging, the framework provides the user with insight on the RTL produced by the HLS tool for each C statement, and permits concurrent hardware and software debugging to discover the first point at which any logic signal in the hardware mismatches with its corresponding variable in software. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Automatic Generation of Parallelized FFT logic for Implementation in FPGA Chips 12

Automatic Generation of Parallelized FFT Logic for Implement...

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12th IEEE international New Circuits and Systems conference (IEEE NEWCAS)

作者： Sokalski, Tayler Manjikian, Naraig Nakina Syst Ottawa ON K2K 2T8 Canada Queens Univ Dept Elect & Comp Engn Kingston ON K7L 3N6 Canada

ISBN: (纸本)9781479948857

this paper considers the automatic generation of parallelized fast-Fourier-transform (FFT) logic for field-programmable gate-array (FPGA) chips. A custom software tool has been created to generate VHDL logic descriptions for parallelized radix-4 FFT architectures using decimation-infrequency (DIF). these architectures accept N simultaneously-provided fixed-point complex-valued input samples every cycle for applications that demand high throughput. Two approaches are described for generating the product terms in complex multiplications involving twiddle constants: standard single-cycle multiplication, and multi-cycle shift-and-add multiplication. Synthesis results are reported for parallelized FFT implementations of different sizes targeting low-cost Cyclone III chips and high-end Stratix III and IV chips from Altera. the shift-and-add approach for constant multiplication is shown to consume more logic resources, but provide a higher maximum clock frequency.

关键词： Clocks Computer architecture Cyclones field programmable gate arrays Hardware Software tools Standards field programmable gate arrays Software Tools cyclones autogeneration Computer Architecture Timing devices Computer hardware Fast Fourier transform Computer chips Formal logic

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An FPGA hardware acceleration of the indirect calculation of tree lengths method for phylogenetic tree reconstruction 24

An FPGA hardware acceleration of the indirect calculation of...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Block, Henry Maruyama, Tsutomu Systems and Information Engineering University of Tsukuba 1-1-1 Ten-ou-dai Tsukuba305-8573 Japan

ISBN: (纸本)9783000446450

In this work, we present an FPGA hardware implementation for a phylogenetic tree reconstruction with maximum parsimony algorithm. We base our approach on a particular stochastic local search algorithm that uses the Indirect Calculation of Tree Lengths method and the Progressive Neighborhood. In our implementation, we define a tree structure, and accelerate the search by parallel and pipeline processing. We show results for six real-world biological datasets. We compare execution times against our previous hardware approach, and TNT, the fastest available parsimony program. Acceleration rates between 34 to 45 per rearrangement, and 2 to 6, for the whole search, are obtained against our previous approach. Acceleration rates between 2 to 4 per rearrangement, and 18 to 112, for the whole search, are obtained against TNT. We estimate that these acceleration rates could increase for even larger datasets. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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A SOLID-GATED GRAPHENE FET SENSOR FOR PH MEASUREMENTS

A SOLID-GATED GRAPHENE FET SENSOR FOR PH MEASUREMENTS

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IEEE international conference on Micro Electro Mechanical Systems

作者： Yibo Zhu Cheng Wang Nicholas Petrone Jaeeun Yu Colin Nuckolls James Hone Qiao Lin Department of Mechanical Engineering Columbia University New York NY United States Department of Microelectronic Engineering Nankai University Tianjin China Department of Chemistry Columbia University New York NY United States

this paper presents a graphene field effect transistor (GFET) nanosensor that, with a solid gate provided by a high-κ dielectric, allows analyte detection in liquid media at low gate voltages. the gate is embedded within the sensor and thus is isolated from a sample solution, offering a high level of integration and miniaturization and eliminating errors caused by the liquid disturbance, desirable for both in vitro and in vivo applications. We demonstrate that the GFET nanosensor can be used to measure pH changes in a range of 5.3-9.3. Based on the experimental observations and quantitative analysis, the charging of an electrical double layer capacitor is found to be the major mechanism of pH sensing.

关键词： logic gates Graphene Electrodes Dielectrics Capacitance Hafnium compounds Liquids

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Pattern-based FPGA logic block and clustering algorithm 24

Pattern-based FPGA logic block and clustering algorithm

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24th international conference on field programmable logic and applications, FPL 2014

作者： Tang, Xifan Gaillardon, Pierre-Emmanuel De Micheli, Giovanni Switzerland

ISBN: (纸本)9783000446450

In classical FPGA, LUTs and DFFs are pre-packed into BLEs and then BLEs are grouped into logic blocks. We propose a novel logic block architecture with fast combinational paths between LUTs, called pattern-based logic blocks. A new clustering algorithm is developed to release the potential of pattern-based logic blocks. Experimental results show that the novel architecture and the associated clustering algorithm lead to a 14% performance gain and a 8% wirelength reduction with a 3% area overhead compared to conventional architecture in large control-instensive benchmarks. © 2014 Technical University of Munich (TUM).

关键词： Clustering algorithms

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Ready PCIe data streaming solutions for FPGAs 24

Ready PCIe data streaming solutions for FPGAs

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24th international conference on field programmable logic and applications, FPL 2014

作者： Preußer, thomas B. Spallek, Rainer G. Technische Universität Dresden Germany

ISBN: (纸本)9783000446450

the PCIe attachment of FPGA accelerators within host workstations is convenient and offers a high-performance direct integration. FPGA-boards designed and equipped as PCIe extension cards are available off-the-shelf. this paper gives an overview on options to provide data streaming abstractions in user applications using PCIe technology. RIFFA and Xillybus are straightforward implementations, which aim at providing ready solutions at this level. this paper will describe these platforms and evaluate them in terms of their ease of use, their perceived maturity and the performance metrics bandwidth and latency. It concludes with providing a brief guideline on how to select the proper platform depending on the usage context. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Portable module relocation and bitstream compression for Xilinx FPGAs 24

Portable module relocation and bitstream compression for Xil...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Beckhoff, Christian Koch, Dirk Torresen, Jim University of Oslo Norway University of Manchester United Kingdom

ISBN: (纸本)9783000446450

this paper presents a novel methodology for generating and compressing configuration bitstreams for modules that can be executed at different positions of an FPGA. the presented methodology for bitstream generation and compression does not need deep knowledge of the bitstream format and it is independent of the target (Xilinx) FPGA family. the approach consists of a design phase where partial bitstreams are decomposed into sequences of module dependent and module independent pieces of configuration data. At run-time, this data can then be recomposed for the individual placement positions by a special DMA configuration controller as one atomic operation without any further software interaction. Our experiments demonstrate that module relocation and fast partial reconfiguration can be implemented at low logic cost. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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