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A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory 24

A logic cell architecture exploiting the shannon expansion f...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Zhao, Qian Yanagida, Kyosei Amagasaki, Motoki Iida, Masahiro Kuga, Morihiro Sueyoshi, Toshinori Graduate School of Science and Technology Kumamoto University Japan

ISBN: (纸本)9783000446450

Most modern field-programmable gate arrays (FPGAs) employ a look-up table (LUT) as their basic logic cell. Although a k-input LUT can implement any k-input logic, its functionality relies on a large amount of configuration memory. As FPGA scales improve, the increased quantity of configuration memory cells required for FPGAs will require a larger area and consume more power. Moreover, the soft-error rate per device will also increase as more configuration memory cells are embedded. We propose scalable logic modules (SLMs), logic cells requiring less configuration memory, reducing configuration memory by making use of partial functions of Shannon expansion for frequently appearing logics. Experimental results show that SLM-based FPGAs use much less configuration memory and have smaller area than conventional LUT-based FPGAs. © 2014 Technical University of Munich (TUM).

关键词： Table lookup

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Biomedical image processing and reconstruction with dataflow computing on FPGAs 24

Biomedical image processing and reconstruction with dataflow...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Grull, Frederik Kebschull, Udo IRI Goethe University Frankfurt Frankfurt am Main Germany

ISBN: (纸本)9783000446450

Increasing chip sizes and better programming tools have made it possible to increase the boundaries of application acceleration with FPGAs. Two applications, localization microscopy and electron tomography, are presented in the author's PhD thesis and summarized in this paper. Both have been ported from imperative languages to the dataflow paradigm that maps well onto long processing pipelines in custom hardware. the results show that an acceleration of 200 compared to an Intel i5 450 CPU for localization microscopy, and an acceleration of 5 over an Nvidia Tesla C1060 for electron tomography while maintaining full accuracy. the main challenge arose from the need to fully understand and re-write most of the imperative source in a form suitable for dataflow computing. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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RAM-based hardware accelerator for network data anonymization 24

RAM-based hardware accelerator for network data anonymizatio...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Yamaguchi, Fumito Matsui, Kanae Nishi, Hiroaki Graduate School of Science and Technology Keio University Yokohama Japan

ISBN: (纸本)9783000446450

Many network services including intrusion detection and recommendation provide their services by analyzing information acquired from network transactions. A careful analysis of these data can reveal valuable information when deep packet inspection is performed. Since these packet analyses generate sensitive information from enormous volumes of transmitted data, the requirement for data anonymization has been discussed. there have been many studies of anonymization techniques and their implementation in software applications. However, limited research has been undertaken regarding hardware-based anonymizers. this paper proposes and evaluates a RAM-based anonymization architecture that maintains both high throughput and a low information-loss ratio. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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An FPGA-optimized architecture of horn and schunck optical flow algorithm for real-time applications 24

An FPGA-optimized architecture of horn and schunck optical f...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Kunz, Michael Ostrowski, Alexander Zipf, Peter Digital Technology Group University of Kassel Kassel34121 Germany

ISBN: (纸本)9783000446450

Optical flow estimation of image sequences is one of the key elements for motion detection. However, processing the optical flow in real-time is still an open task due to its computationally expensive nature. In this paper we present an FPGA-optimized architecture for optical flow estimation based on the algorithm of Horn and Schunck. While existing FPGA-realizations are only partly real-time capable, on a Stratix IV our architecture enables the computation of the optical flow for each pixel of a frame with 640 × 512 pixels at a framerate of 30 fps in iterative and up to 4k resolution (4,096 × 2,304 pixels) at a framerate of 20 fps in full-pipelined form. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Adaptive linear predictor FIR filter based on the Cyclone V FPGA with HPS to reduce narrow band RFI in AERA radio detection of cosmic rays

Adaptive linear predictor FIR filter based on the Cyclone V ...

引用

international conference on Advancements in Nuclear Instrumentation Measurement Methods and their applications (ANIMMA)

作者： Zbigniew Szadkowski D. Glas Department of Physics and Applied Informatics University of Łódź Łódź Poland For the Pierre Auger Collaboration University of Łódź Łódź Poland

ISBN: (纸本)9781479999194

We present the new approach to a filtering of radio frequency interferences (RFI) in the Auger Engineering Radio Array (AERA) which study the electromagnetic part of the Extensive Air Showers. the radio stations can observe radio signals caused by coherent emissions due to geomagnetic radiation and charge excess processes. AERA observes frequency band from 30 to 80 MHz. this range is highly contaminated by human-made RFI. In order to improve the signal to noise ratio RFI filters are used in AERA to suppress this contamination. the filter has been already tested in the real AERA radio stations on Argentinean pampas with a very successful results. the linear equations were solved either in the virtual soft-core NIOS® processor (implemented in the FPGA chip as a net of logic elements) or in the external Voipac PXA270M ARM processor. the NIOS®R processor is relatively slow (50 MHz internal clock), calculations performed in an external processor consume a significant amount of time for data exchange between the FPGA and the processor. Test showed a very good efficiency of the RFI suppression for stationary (long-term) contaminations. However, we observed a short-time contaminations, which could not be suppressed either by the IIR-notch filter or by the FIR filter based on the linear predictions. For the LP FIR filter the refreshment time of the filter coefficients was to long and filter did not keep up with the changes of a contamination structure, mainly due to a long calculation time in a slow processors. We propose to use the Cyclone®R V SE chip with embedded micro-controller operating with 925 MHz internal clock to significantly reduce a refreshment time of the FIR coefficients. the lab results are promising.

关键词： Contamination Finite impulse response filters Cyclones field programmable gate arrays Cosmic rays Detectors Mathematical model

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Methods for implementation of feedback loops in high speed FPGA applications 24

Methods for implementation of feedback loops in high speed F...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Safari, Nima Mauer, Volker Gheitanchi, Shahin Wireless SSE Altera Corporation High Wycombe United Kingdom

ISBN: (纸本)9783000446450

In many Digital Signal Processing (DSP) modules, increasing the number of pipelining stages to achieve higher throughput may break the module functionality if a feedback-loop exists in the algorithm. this paper addresses a novel algorithmic-level technique to modify implementation of feedback loops to allow deeper pipelining while sustaining the module functionality. An equivalent model for a first-order Infinite Impulse Response (IIR) filter can be obtained by a cascade model including a higher order repeated-pole IIR filter followed by a Finite Impulse Response (FIR) filter. the order of the repeated-pole IIR filters, and hence the number of pipelining stages can be chosen to meet the Fmax requirements. the model is further developed to include a class of mathematical recursive functions to cover many different DSP applications. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Low-cost multiplier-based FPU for embedded processing on FPGA 24

Low-cost multiplier-based FPU for embedded processing on FPG...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Pasca, Bogdan Altera European Technology Centre United Kingdom

ISBN: (纸本)9783000446450

Industrial applications often require processing data with large dynamic ranges at low sample rates. As algorithms become more complex, handling the data range of variables required for fixed-point implementations becomes time consuming, and can also lead to inefficient designs. Floating-point solutions leverage these limitations trading automatic data range handling for a usually higher implementation cost. the adoption of floating-point solutions for this class of applications is conditioned by area and performance requirements. In this paper we present a low-cost floating-point unit which can either be used standalone, or can be attached to a RISC microprocessor. the proposed unit targets modern, multiplier-based FPGAs, computes efficiently costly operations: ×, ÷, 1/x, √x and 1√x, requires less than 700LE and 4-9bit multipliers on a CycloneIV and runs close to 150MHz. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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FPGA implementation of a multi-algorithm parallel FEC for SDR platforms 24

FPGA implementation of a multi-algorithm parallel FEC for SD...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Wu, Zhenzhi Liu, Dake Yang, Zheng Wang, Qingying Zhou, Wei School of Information and Electronics Beijing Institute of Technology Beijing100081 China

ISBN: (纸本)9783000446450

Forward Error Correction (FEC) consumes excessive computation in a Software Defined Radio (SDR) system. In this work, a high-throughput flexible FEC processor is proposed for the decoding acceleration. the FEC processor enables Turbo/QC-LDPC/Convolutional Code decoding with software-hardware co-reconfigurability. A multi-algorithm unified trellis processing unit is introduced for resource sharing. A parallel architecture is proposed for high-throughput decoding. the Software Defined FEC (SD-FEC) with Application Specific Instruction-set Processor architecture is introduced for improving flexibility and enabling fast reconfiguration. the proposed SD-FEC can be applied to both low-cost low power applications and high performance applications. Results show that the proposed tri-mode FEC processor achieves high decoding efficiency and enough flexibility, which suits for the flexible SDR platforms. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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A mixed integer linear programming approach for design space exploration in FPGA-based MPSoC 24

A mixed integer linear programming approach for design space...

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24th international conference on field programmable logic and applications, FPL 2014

作者： Dammak, Bouthaina Benmansour, Rachid Niar, Smail Baklouti, Mouna Abid, Mohamed LAMIH University of Valenciennes Valenciennes59300 France National School of Engineers of Sfax Sfax3042 Tunisia

ISBN: (纸本)9783000446450

Heterogeneous Multiprocessor System-on-Chip (Ht-MPSoC) architectures represent a promising approach as they allow a higher performance/energy consumption trade-off. In such systems, the processor instruction set is enhanced by application-specific custom instructions implemented on reconfigurable fabrics, namely FPGA. To increase area utilization and guarantee application constraint respect, we propose a new architecture where Ht-MPSoC hardware accelerators are shared among different processors in an intelligent manner. In this paper, a Mixed Integer Linear Programming (MILP) model is proposed to systematically explore the complex design space of the different configurations. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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Robust and flexible FPGA-based digital PUF 24

Robust and flexible FPGA-based digital PUF

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24th international conference on field programmable logic and applications, FPL 2014

作者： Xu, Teng Potkonjak, Miodrag Computer Science Department University of California Los Angeles United States

ISBN: (纸本)9783000446450

We have developed the first FPGA-based digital physical unclonable function (PUF) by leveraging the reconfigurability of an FPGA and introducing a new way of using the standard analog delay PUF. the key observation is that for any analog delay PUF, there is a subset of challenge inputs for which the PUF output is stable regardless of operation and environmental conditions. We use only such stable inputs to initialize the look-up tables (LUTs) that are configured in such a way that the digital PUF is formed. We demonstrate the effectiveness of the new security primitive using extensive simulation and experimental results. For example, we show that the new PUF is resistant against a wide spectrum of security attacks and its output stream passes all the NIST randomness tests. © 2014 Technical University of Munich (TUM).

关键词： field programmable gate arrays (FPGA)

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